Feb 12 2010

3D Packaging brings New Design Challenges

Published by at 1:14 pm under Uncategorized

Multi-Die packaging is one of the newer areas for co-design.  Space and function concerns are driving the multi-die assembly in the Z-axis direction.  There is a lot of activity in determining both engineering solutions and cost of production solutions for this space as was evident from the number of papers presented at this week’s ISSCC event.
The area of 3D assembly involves many options including die on die with bond wires, die on die with bump, package on package, and TSV (Thru Silicon Vias).  Each of these methods has benefits and tradeoffs in performance, price and reliability.  TSV technology also has several methods, an in-process solution and a a post-process solution.  As there is no standard IP interface between multiple die for assembly, these interface between logic, memory and analog signal paths on these chip have to be analyzed for DFT, thermal, DC &AC parametrics, and timing conformance with hand assembled CAD tool flows and engines.
Knowing that die with be subjected to thinning and scribe lane modifications for multi-die assembly vs single die assembly, impacts the design rules used in the layout of the Ics involved.  CAD Tools addressing these early stage 3D issues are severely lacking in the commercial sector.  Without the support from tools, the community relies on the engineering standard of experience and education.  To help with this process, the MEPTEC Chip to System Symposium in Feb, is having a presentation by Jan Vardaman on the tradeoffs in the various 3D assembly options and information on how to select the best fit for an appliation.
The symposium also features a session lead by Gary Catlin of Plexus,  whose semiconductor experience has been continuous for over 40 years. His session focuses on available CAD tools that can be cross-utilized for 3D assembly and multi-die packing as well as design practices that should be used.  These tools and techniques are focused on addressing the yield and reliability of the end packaged system through high volume production.  The session includes a Mentor Graphics presentation on BIST and DFT for mult-die systems, by Sigrity, Inc on SI and power design/delivery aspects of the system, and on thermal modeling by CAD Design Services.  At Plexus, Gary works with customers on complete end-to-end product design and implementation solutions for commercial and industrial multi-die applications.
PC

Multi-Die packaging is one of the newer areas for co-design.  Space and function concerns are driving the multi-die assembly in the Z-axis direction.  There is a lot of activity in determining both engineering solutions and cost of production solutions for this space as was evident from the number of papers presented at this week’s ISSCC event.

The area of 3D assembly involves many options including die on die with bond wires, die on die with bump, package on package, and TSV (Thru Silicon Vias).  Each of these methods has benefits and tradeoffs in performance, price and reliability.  TSV technology also has several methods, an in-process solution and a a post-process solution.  As there is no standard IP interface between multiple die for assembly, these interface between logic, memory and analog signal paths on these chip have to be analyzed for DFT, thermal, DC &AC parametrics, and timing conformance with hand assembled CAD tool flows and engines.

Knowing that die with be subjected to thinning and scribe lane modifications for multi-die assembly vs single die assembly, impacts the design rules used in the layout of the Ics involved.  CAD Tools addressing these early stage 3D issues are severely lacking in the commercial sector.  Without the support from tools, the community relies on the engineering standard of experience and education.  To help with this process, the MEPTEC Chip to System Symposium in Feb, is having a presentation by Jan Vardaman on the tradeoffs in the various 3D assembly options and information on how to select the best fit for an appliation.

The symposium also features a session lead by Gary Catlin of Plexus,  whose semiconductor experience has been continuous for over 40 years. His session focuses on available CAD tools that can be cross-utilized for 3D assembly and multi-die packing as well as design practices that should be used.  These tools and techniques are focused on addressing the yield and reliability of the end packaged system through high volume production.  The session includes a Mentor Graphics presentation on BIST and DFT for mult-die systems, by Sigrity, Inc on SI and power design/delivery aspects of the system, and on thermal modeling by CAD Design Services.  At Plexus, Gary works with customers on complete end-to-end product design and implementation solutions for commercial and industrial multi-die applications.

PC

One response so far

One Response to “3D Packaging brings New Design Challenges”

  1. # Ed Malloyon 11 Jun 2010 at 2:26 pm

    It was an interesting Symposium and the latest IMS3TW conference was another opportunity to delve into these crtical topics.

    Ensuring the right test infrastructure is inserted during logic design combined with methods for ensuring high-quality silicon with fewest test escapes will be an important trade-off in order to capture the potential value of 3D Stacking or 3D SIP.

    Thx
    Ed Malloy
    Cadence Design Systems

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