Pallab’s Place

At Game Developer Conference, Sony introduced thier new motion controller for the Playstation called “Move”.  It is similar in function to the remotes the Nintendo Wii, but utilize a 3 Axis Gyroscope and a 3 Axis Accelerometer with higher sensitivity to the Wii controller.  The Move controller works in partnership with a camera system (Playstation Eye) and a colored globe that is at the end of the controller.  The combination of the MEMS control and the optics system provides a perceived faster response (sub 1 frame of latency) than the Wii motion plus, but with the same feedback and accuracy. The experience was based on using the controller on a number of pre-alpha software titles, so things may improve and change as the games improve and are finalized to utilize the device.

The Move controller, it’s associated “wireless sub controller” and the Playstation Eye are all powered via the USB interface on the Playstation.  The Move and it subcontroller also charge through the same USB cable connections.  For some high movement games, the controllers can be combined so a single user uses two (2) of the Move controllers to map the game play rather than a controller and a sub-controller.

PC

Importance of low power has never been more pronounced as with this year’s ISSCC. Low power designs were highlighted in number of sessions throughout the conference. Some of the memorable ones were from Intel on the application of DVFS technique to 80-core processor, the clock power reduction using pulse latches in Power 7 by IBM and low power techniques applied to the AMD 32nm processor (Bulldozer?).

These processors highlight significant improvements in the application of low power techniques on real designs. Such real world design practices should encourage more interest in this area and enable some of the difficult techniques to be realized in silicon.

Low power techniques are always built on simple principles. For example, making prudent choices for architecture like limiting the bandwidth, not redoing tasks that are completed, and working only when needed are simple principles which should reduce the overall power consumption. Yet, implementation is quite complex because of the integration demanded in the modern processors and other design-imposed limitations. As we know that with every subsequent process migration, transistors are becoming cheaper. Designers would make use of these transistors by either performing more computations (multi-core) or integrating more functions. If the designers are not careful with defining the architectures, power inefficiencies can exists.

The first paper from Intel (session 9.01) studied the effect of DVFS technique on 80-core 65nm NOC processor. The processor was devised such that each of the 80-cores can be voltage and frequency controlled all the way to shutting down completely. The measurement was conducted with varying loads of traffic. Intel used proprietary scheduling techniques to come up with voltage and frequency numbers for each processors based on the load. The results were fairly intuitive that voltage variation had a bigger effect on power than the frequency variation (voltage is the square term in the power equation).

The second paper (session 9.03) highlighted some of the interesting low power concepts applied to the Power7 architecture. Power 7 designed in 45nm SOI process uses pulse clocking in order to save power. They use full master-slave configuration, but keep the master stage ON at all times during the pulsed mode operation. Data flows through the master stage and only slave stage is used for storage. For testing purposes, the master stage functionality is restored. IBM reported about 20% power savings by employing this technique.

AMD’s processor (session 5.06), designed in 32nm SOI process had several new low power techniques implemented. AMD presented two power saving techniques and one for on-chip power measurement. The first method was to control clock power which contributes ~30% of power. To control clock power, AMD did a careful clock gater placement and implemented fine grain and multi-stage clock gating. Secondly, it used power gating throughout to control the power with shutting down the processor. AMD got away using footer devices because of the SOI process.  And finally AMD designed a circuit to monitor power by monitoring a few of the critical signals for activity.

Overall, there has been rich low power design content in this year’s ISSCC. Readers can check out the proceedings for other interesting papers. After a forgettable 2009, this year has started a lot better and seems like the low power designs are back on track. This has increased our hopes of seeing more and more low power designs in future conferences.

AI

At the MEPTEC Chip to System symposium there a lot of discussion about the silicon that fits in the packages in addition to the package.  The opening keynote from Tom Gregorich framed the conference with the premise that chip scaling is going to be limited by the reality that sometimes users need to put the analog/MEMS and the digital/memory functions together in a single package and they can’t be built on the same chip due to technology differences and cost.  These are a combination of design, fab, test and assembly costs.

One of the drivers in the packaging arena is package size and pin pitch.  The form factor for many devices are driving the investigation of tight package pitches down to 0.3mm per pin, however these have a drawback of expensive PCBs and board level assembly, as well as thermal dissipation issues.  On the scaling side, Cisco presented another design tradeoff issue for networking Ics.  For higher data rates and throughput, they are pushing the process envelope to smaller geometries, and more parallel data processing (more channels per chip).  This is creating a pin count explosion and a heat dissipation per unit area issue with the die.  Cisco indicated that they are currently building 20mm/side die, and would like to go larger to address getting all the pins on and spreading the heat out, but they are running in to the litho field size and yield with these large die.  One of the areas to help with these issues is the development of low loss power delivery methods between PCB and die with the associated increase in thermal density handling.

Additional speakers discussed the 3D assembly techniques focusing on handling challenges for very thin (20um thickness) 300mm wafers that have been mechanically backlapped for TSV assembly.  These issues include die separation, particle defect creation and post-thin testing.  The discussion was then carried forward to the topic of BIST, scan development and post assembly testing for systems with TSVs and accessability issues to embedded and burried functions in the internal die stacks of the TSV modules.  The forecast for TSV in production is 2012 for DRAM for server applications, 2013 for use in FPGA/Memory systems, and 2014 for microprocessor/ memory applications,  From a die stacking approach, non-TSV die stacking wafers presented as a current high volume technology with over 2.5B stacked memory modules have been shipped with 2 to 8 die.  The technology has been shown to support up to 17 die stacks in R&D.

The conference ended with an open panel discussion (the panel session was open to the public, not just registered attendees) on patent and IP issues.  The lively discussion included protection in the US and Japan vs India/China policies and realities, patent trolls, and the new vehicle – the patent agitator.  This vehicle is typically a law firm or licencing organization that buys or becomes a licensee of key technology patents in bulk, and then re-licenses the entire portfolio in “insurance” mode to companies that may end up with infringement issues and are not in a position to individually negotiate and license hundreds to thousands of patents for a given project.

PC

At the SPIE Advanced Lithography Conference, updates on NanoImprint technology, eBeam and Self Assembly techniques were presented that were all confident that EUV would be pushed out until the 16nm process node at the earliest.  In addition to new equipment (such as the Nikon NSR-S620D) and techniques for double & quad patterning, it was clear that optical and existing technologies for lithography through the 22nm node were the solution of choice.  While EUV has made progress in the recent past, the cost and throughput were still sited as major issues.

Several universities and Molecular Imprints presented papers on the recent advances in NanoImprint Lithography (NIL).  Molecular discussed their NuTera HD7000 system which is tarted to the disk drive and patterned media market.  The tool is a very high throughput (>300 double sided dph at field size up to 95mm [3.5inch]) while maintaining a sub 25nm resolution.  The new machine is about half the footprint of its previous 150dph machine and is shipping in 2010.  Molecular has sold 13 of these systems to five drive customers including Hitachi.   The new technology is currently in the 800+Gb//in sq density range and they have a roadmap to address the over 4Tb/in sq range in the future.

To accompany the new printer, they announced installation of thier Perfecta TR1100 template printer.  One of the previous limitations on imprint technology was the long creation time of the templates and their associated wear cycle.  The new template printer can create 10 templates/hr (equiv of a “soft tool” for the prototype world) for production use vs the greater than 1 week turnaround for a traditional Gaussian e-beam created master (equiv of a “hard tool” for the prototype world).  These template printers have also been installed at traditional masking companies such as Hoya.

On the semiconductor side, their Imprio 300 printer is now providing 4 wph throughput while allowing for mix and match overlay accuracy to a 193i layer of better than 20nm for applicability to current CMOS memory use.  DNP has purchased thier mask replication tool for use in 24nm half-pitch applications.

D2S and the eBeam Initiative announced application of their direct write on wafer technology using character shaped beams (DFEB) to mask making.  As their technology advances for wafer throughput, they applied the technology to mask mastering and achieved a combination of higher design accuracy on via and cell printing, while maintaining the current wafer throughput.  The new application is being investigated and tested by current members DNP and Toppan.  As a result, they announced that several customers and inspection profivers have now joined the initiative including Global Foundries, Samsung, KLA and Jeol.

One of the most crowded sessions was on Self-Assembly (SA) techniques and materials.  This session was dominated by papers from IBM. The results indicated that “bounding” and “guide” techniques for the SA materials in the 5-6nm feature size, could be used to create usable lines and hole patterns (devices/interconnect and vias) for 22nm node half pitch applications.  They presented preliminary results that indicated these techniques were extensable to use at 16nm nodes and further delay the need for EUV.  The major advancement was the rapid formation of the structures moving from close to 1 hour assembly times to the 1-5minute time frame.

PC

The 11th Annual International Symposium on Quality Electronic Design (www.isqed.org) and the 1st Annual International Solar Energy Technology Conference (www.isetc.org) have finalized their programs for March 22-24, 2010.

The ISQED conference is once again featuring a full day of tutorials on the theme of Design Technologies and Opportunities in the Nano-Scale Era, and embedded tutorials on the use of field solvers in both IC and System Level design, and Parasitic Extraction.  The conference has 24 sessions in 4 parallel tracks over the next two days.

Once again, the conference is holding an evening panel discussion and dinner.  This years panel is on the subject of design methods for long life cycle and is moderated by Tets Maniwa.  There are a total of 7 keynote speakers – the lunch keynote is by Antun Dominic of Synopsys, and the morning Plenary sessions have talks from Inphi, Cadence, Denali, HelloSoft, Mentor, and D2S/eBeam Initiative.

Discounted registration is available through March 9th, and the FREE registration for attending the exhibits and poster session will open soon.

The ISETC event is new and is also being held at the Doubletree Hotel in San Jose concurrent with the ISQED event.  It is focusing on the technology behind capturing and use of energy from solar rays.  The inaugural conference features speakers from both academia and industry including such luminaries as Dr. Ted Kamins of Stanford, Dr. J Campbell Scott of IBM Research, and Dr. Homer Antoniadis of Innovalight.  The first year conference is a one day event featuring nine speakers.  Advanced registration is currently available at the site.

PC

Multi-Die packaging is one of the newer areas for co-design.  Space and function concerns are driving the multi-die assembly in the Z-axis direction.  There is a lot of activity in determining both engineering solutions and cost of production solutions for this space as was evident from the number of papers presented at this week’s ISSCC event.

The area of 3D assembly involves many options including die on die with bond wires, die on die with bump, package on package, and TSV (Thru Silicon Vias).  Each of these methods has benefits and tradeoffs in performance, price and reliability.  TSV technology also has several methods, an in-process solution and a a post-process solution.  As there is no standard IP interface between multiple die for assembly, these interface between logic, memory and analog signal paths on these chip have to be analyzed for DFT, thermal, DC &AC parametrics, and timing conformance with hand assembled CAD tool flows and engines.

Knowing that die with be subjected to thinning and scribe lane modifications for multi-die assembly vs single die assembly, impacts the design rules used in the layout of the Ics involved.  CAD Tools addressing these early stage 3D issues are severely lacking in the commercial sector.  Without the support from tools, the community relies on the engineering standard of experience and education.  To help with this process, the MEPTEC Chip to System Symposium in Feb, is having a presentation by Jan Vardaman on the tradeoffs in the various 3D assembly options and information on how to select the best fit for an appliation.

The symposium also features a session lead by Gary Catlin of Plexus,  whose semiconductor experience has been continuous for over 40 years. His session focuses on available CAD tools that can be cross-utilized for 3D assembly and multi-die packing as well as design practices that should be used.  These tools and techniques are focused on addressing the yield and reliability of the end packaged system through high volume production.  The session includes a Mentor Graphics presentation on BIST and DFT for mult-die systems, by Sigrity, Inc on SI and power design/delivery aspects of the system, and on thermal modeling by CAD Design Services.  At Plexus, Gary works with customers on complete end-to-end product design and implementation solutions for commercial and industrial multi-die applications.

PC

I recently had a chance to have a conversation with Judy Priest of Cisco about some of the design and packaging issues for accepting and qualifying new SOCs for high speed networking applications.  Historically, the high end network packages were being designed and selected as both heat spreaders and pitch spreaders between the IC pad pitch and those of the interconnect on the PCB.  This has changed in a current era of board level signals >20GHz and power supplies below 1V.

In order to meet these performance specifications, these networking systems have become very large die (around 20mm/side) and these are in packages occupying 55mm/side.  These can be either single die systems, multiple die arranged in a planar fashion in a single package cavity or thinned and stacked die in one package.  For single die systems, the package configuration has a great deal of influence on the placement and separation of voltage islands, and global placement of power down blocks and functions as dictated by the bond wire and board level signal integrity requirements. For multi-die systems, these same issues as well as data pattern based thermal management inside the package environment is also a key design element that needs to be fed back to the IC design as a floor plan constraint.  Stacked die (traditional, not TSV based) and very large single die have these same design constraints in addition to package and die / package warpage and material stress issues.  The warpage and stress that is in the package is variable based on the density and material used for the different styles of current generation HiK and Lead free packages.  These two effects can cause differences in the leakage power and timing  performance of the die since it mechanically changes the planarity of the silicon substrate.

Most high speed networking products are being deigned for 10yr+ die and package/bond reliability.  This brings back to the chip design and architecture level the final assembly criteria of die thickness, pad size and reliability for wire or bump bond, shock survivability from a drop test and wave solder/post assembly high temperature processing (a known susceptibility for technologies such as PCM memory).

Judy will be discussing these and more details about design tradeoffs between package and die at the MEPTEC Chip to System Symposium (http://www.meptec.org/meptecfromchipto.html) being held in San Jose at the end of February.  With the invasive nature of the need for high speed connectivity in most of today’s systems and SOCs, is driving package interaction from a niche issue to being a mainstream concern very quickly.

PC

One of the key components of the audio systems (amplifers, guitars, mixers, etc) are the knobs and sliders.  Continuing their long history in the potentiometer business, they are re-issuing classic products and bringing out new products for new applications.

On the classic side, they have reissued the Model 82 Vintage Premium Guitar Potentiometer.  The new pot is now RoHS compliant, has the same low noise performance as the original from 1977 and features a 100,000 turn rotational life.  This is the classic guitar and bass tuning knob used with Seymore Duncan pickups on Fender Signature Series guitars.

On the new products side, they have added new RoHS compliant Resistive Sliders for the audio and broadcast mixer market.  These sliders are motorized with built in servos and are available with and without the built-in data converter.  They feature a long life carbon element and support either PC terminals or a snap-in connector option.

New products in the low noise, RoHS compliant line are manual sliders for mixing boards, and for solid state and tube amplifiers are forth coming.  All of these parts are designed to maximize the Quality and Reliability.  The targeted life cycle in use at the application is 20+yrs, for this reason, testing and quality assurance are hallmarks of these parts.

They are in the process of developing new potentiometer technology based on non-contact magnetic materials.

PC

This years NAMM show, and some carryover from CES, was heavily focused on making use of the advanced processing & storage capabilities available in very low power form factors.  The result was Generation 3.0 of advanced sampling and modeling systems that now using the full data bandwidth and signal handling features that are available in standard components for both the consumer and industrial marketplace.

The Generation 1.0 was started back in the 1960’s with the analog based sampling, effects and modulated playback that was defined by the Moog Synthesizer invented in 1964 by Bob Moog.  To honor this starting place, the NAMM show and The Bob Moog Foundation displayed some key artifacts, equipment and material from the Waves of Inspiration: The Legacy of Moog exhibition which is running from August 29, 2009–April 30, 2010, at the Museum of Making Music’s facilities in Carlsbad, California.

The Generation 2.0 was the long cycle, still on-going, of sampled music and sampled MIDI/VST instruments that ranged from rudimentary low resolution data to high accuracy single note and single sound samples at mid level data rates. These digital solutions were targeted at moderate capability portable and stage devices, based on power limitations, and high quality capability has been reserved for desktop/studio platforms.  These generation 2.0 solutions were still prevalent in existing digital products from Yamaha, Roland, Sony hardware and software from Garritan, Calkwalk, Native Instruments, and Garage Band.  Yamaha introduced a MIDI audio-visual device designed by renowned artist Toshio Iwai.  The device is shown in the following photo, and is an interactive art piece that has 256 programmable LED buttons that can display patterns and play music in the modes of up to 64 simultaneous samples at once.  The features and SD card and MIDI interfaces and utilizes dual 32 bit embedded processors on a custom (linux based) OS.  The music can be programmed as full songs, or in draw mode, fully interactive with sounds based on touch interface with the LED keys.

Tenori-on Orange

The Generation 3.0 is now starting and is characterized as utilizing the full capability of 2010 era mobile and studio digital processing as well as “musical sampling”.  “Musical Sampling” is the concept and the capture of instrument sounds and effects, NOT on a standalone note basis, but in context of other notes and chords, and materials of the instruments.  The Generation 3.0 has been in place for a little while, promoted by Line6 with their DSP based solid state modeling amps which recreate historic tube amplifiers, and Roland with their V-Series of instruments.  Roland continued to expand thier V-series instruments with a new electronic drum kit and components, a new drum pad (the Octapad). a V-series combo piano/organ, and a new low priced and simple interface voice processor (VP-7), in addition to their existing keyboard line.  The V-line of equipment is migrating from stored samples as the playback method, rather they have created continuous time and multi-note correlated models for the notes, chords and phrases being played back.  Following this technology, the VP-7 is small effects box that takes a microphone input (through an XLR connection) and a MIDI interface from a keyboard, and then generates vocal harmonies as either female choir, kids choir, Gregorian choir, jazz scat, duet or trio in real time, for use in live performance environments, based on both the notes sung by the vocalist and the chords played on the keyboard.  Previously, these products were only available as studio products in the several thousand dollar range, the VP-7 is a small form factor accessory in the several hundred dollar range.  A demo is available at http://www.rolandus.com/products/productdetails.php?ProductId=1062

Yamaha also has introduced a new line of stage pianos and electronic drum systems.  These incorporate phrase and context based samples as well as new materials.  The drums have new electronic heads that are both more responsive and sensitive.  The keyboards feature new weighted keys that are almost indistinguishable from those used on their concert grand acoustic pianos.  The keyboards also supports full modeling of the hammers, pedals, and both adjacent and non-adjacent keys being used simultaneously and the harmonics generation on the sound board.

The drop in price, capacity and performance for external HDDs has made them the new preferred distribution format for the sampled and modeled instruments.  The availability of this format (typically a 60GB-1.2TB distribution) has allowed for a new form of sampled data.  The resolution is higher at 24bits/96K or 24bits/192K sampling.  In addition to traditional “note” based information, context, phrase based, “grove based”, and equipment options are now part of the environment.  On the equipment side, it is not only effects and amp modeling, but on band instruments there are also options.  On the band instrument side it includes wood and metal mutes for brass instruments, different mouthpiece types for woodwinds and both current and classic drum kits and cymbals.  PG Music’s Band in a Box product is shipped on a 160GB USB HDD for their complete “chord based” music samples in compressed format.  Their full “audiophile” lossless product has the samples in an uncompressed format that is suitable for professional studio application is shipped on a 1.5TB USB HDD.

Following this trend toward more realistic sound, for percussion Sonic Reality has introduced “Epik Drums – a Ken Scott Collection”. Ken is the legendary British recording engineer and producer who recorded The Beatles, David Bowie, Elton John, Supertramp, Pink Floyd, Jeff Beck, Mahavishnu Orchestra, Dixie Dregs, Devo, Lou Reed, America and many other iconic artists.  The new virtual instrument plug-in contains 80GB of 24 bit drum samples recorded in multi-track as a combination of audio grooves and MIDI kits.  These samples were recorded from authentic historic drum kits and configurations by top drummers Billy Cobham, Bob Siebenberg, Terry Bozzio, Woody Woodmansey and Rod Morganstein as they played on the original albums.

Ken Scott - Epik Drum

To utilize these new samples and virtual instruments, the folks at Eigenlabs (UK) have created a new performance oriented instrument called the Eigenharp.  It is available in three models the Alpha (top of the line, largest, professional market), the Pico (smallest, consumer product) and the new Tau (middle).  The instrument has patented 3D position sensitive keys, pressure sensitive resistive strip controllers, and a breath pipe controller that act as the programmable and playback surface for the device.  The three models differ in the number and type of control keys (standard and percussive), number of strip controllers and finishes.  Using the instrument the musican can play and record loops, change scale and key, transpose, alter tempo, program beats, create arrangements, switch and layer multiple sounds, all while the musician is performing live on stage.  A photo of the Eigenharp Alpha follows.

Eigenharp Alpha

Another instrument that is getting new modeling capabilities are the guitar and bass.  Brown’s Guitar Factory (Minnesota) has been building custom electric basses for several years.  Recently they created a Kahler bass tremolo system with acoustic and MIDI saddles that can track and sound as accurate as the best performing keyboard synthesizers on the market. They are offering this as a conversion kit and as a 4 string acoustic-MIDI electric bass.  It can be played as a standard bass or through a modeling system to act as a full synthesize controller.  On the guitar side, Gibson introduced thier 3rd generation auto-tuning guitar – The Dusk Tiger.  Once again, based on the Les Paul solid body guitar, the auto-tuning system features improved PZT controls for the tuning heads, a new re-chargeable battery configuration, and a modeling systems that can be downloaded into the guitar.  Using the supplied software, you can program the guitar to different tuning modes, to sound like different pickups and guitar models.  The new control knob also supports several standard classic guitar models as standard loaded in the guitar.  As in previous models, the guitar is targeted as a stage performance instrument, so at playback, just a standard guitar amp is used through the 1/4″ jack and it is played normally.

The last area that saw improvement in dynamic range and sonic reproduction was in the area of headphones and earphones.  Ultimate Ears (now a Logitech Company) has been making in-ear custom monitors for touring musicians and sound engineers for over 12 years.  Using advanced sound guide design, custom cross over circuits, and state of the art COTS speakers, they were presenting custom molded duel ear monitors with 2 to 6 speakers, including sub-woofers.  The custom ear molds insure that there is sufficient sound isolation from the ambient environment to allow the performers to hear the playback they need during live stage performances.  These in-ear monitor systems feature a frequency response of 20hz-18KHz and input sensitivities up to 124dB @ 1mW, and 26dB of noise isolation.  These are typically professional level products, however their intro level product is a dual speaker system that is price compatible with most DJ level and home studio over the ear headphones.

On the consumer side there several new in-ear speaker systems from Monster Cable.  Based on their experiences with the Dr. Dre “Beats” headphones from Monster Cable,  Erin Davis (Miles Davis’s son) and Vince Wilburn Jr (Miles Davis’s nephew) approached Noel Lee about making a headphone for the Jazz marketplace.

Erin Davis

Vince Wilburn Jr.

Working with the group at Monster they created the Miles Davis Tribute in-ear speakers that are derivative of the Turbine in-ear speakers released in 2009.  In order to test and qualify the product, in addition to standard testing, they also sought feedback from artists who have been in Jazz for a long time and some of whom played with Miles.  One of the people reviewing the product was Lenny White who played with Miles on the seminal album “Bitches Brew”, is the drummer for the Jazz-Fusion defining group Return to Forever, and has recorded and played with artists from just about every genre.

Lenny White

In addition., to the Miles Davis in-ear speakers, Monster also released the Turbine Pro Copper product with is an upgraded version of the Turbine in-ear speakers featuring enhanced bass, and a faster response time for improved clarity at the high frequencies.  The Pro product is more of studio class / audiophile product than the Turbine speakers.  The new ear buds improve sound isolation, so the in-ear product behaves in the same class as a traditional over the ear product.

The summary from the show was that now that processing power is available in mobile and low power platforms, the environment to musically capture, playback and monitor high performance audio, based on a digital signal path, is at levels nearly inpercetibly different from traditional analog (strings, woodwind and brass) instruments.  This adds a new dimension to the ability to distribute music and adds another dimension of creativity to the traditional musician to explore new music and styles anywhere / anytime.

Peter Chatterjee and Pallab Chatterjee

Recently there have been several blogs, emails and articles from people talking about benchmarks in DRC/LVS/RCE/Appl Rules (general class of Physical Verification or PV tools) and some of those were run using runsets from vendor A on tools from vendor B.  These benchmarks were created to show “whose’s tool is the biggest and best” in the continued posturing war between EDA vendors.   As a result of this ritualistic posturing and “fanning of their plumage (benchmarks)” a large portion of the design community cannot correctly identify use models or selection criteria for these tools.

To help out in this situation, here are some basic information to understand and some questions to ask when reviewing information or statistics on PV tools.  For the sake of simplicity, I will be discussing issues with respect to Design Rule Checking (DRC), there are similar but different guidlines for LVS, ERC, RCE, and Application Rules Checking.

The first thing to understand is that there are several categories of design rules available from a wafer fab – (A) the basic structure rules, (B) yield and reliability rules, ( C) device operation rules, (D) suggested design rules, (E) optional design rules, (F) I/O rules, (G) power rules and (H) DFM/Litho rules.  Design rule sets for larger geometry processes (>0.35um)could typically be described in under 250 rules, most modern processes have upwards of 2000 rules a large portion of which are context based.  Signoff qualification for the right to release a design to a wafer fab usually includes passing ALL of the rules (A-H) being released by the fab.  The runset(s) are qualified on test data & real designs, validated for a specific version and mode of BOTH the parser and code, and released for specific minimum hardware platforms/configurations and operating systems.

To put the qualification effort into practical terms, based on the creation of several hundred PV runsets I have created/been involved with the creation of: for a typical layer on a 40nm process (e.g. diffusion or Metal 1) the basic design rules include minimum width and size, if bends are allowed, and parallel line spacing to the same layer or adjacent layers and use only simple boolean operations and “generation 1″ verification rules.  These “generation 1″ rules have existed since Maskcap/GPL days (1970’s) and are supported by pretty much every tool on the market.  These rules take about 4 hours each to validate between the creation of the test case, running it on the software, verifying the results as only errors being flagged, and getting signoff from CAD / design / process engineering and moving the code to a releasable area.,

The balance of the rules tend to be coded with syntax that is described in the EDA companies documentation about the function inside of their tool, but the implementation and algorithms used are different in each tool.  Hence the operation, flag location and aspects of checked objects (projections, vertices, edges) may be different in different modes (flat, hierarchical, dynamic) as well as in different tools.  These rules tend to have test cases that are in blocks cut from real designs, rather than created from standalone test cases.  Hence, these rules as coded in the complete runset take about 6 hours each for the validation loop.  For a typical 40nm process the 2000 rules consume about 11,200 man hours to validate for wafer release/signoff quality approval for the first software tool, and about 60% of that (6,720 man hours) for subsequent tools, as the test cases are already done.

With this extent of an effort behind the release of a runset for use, for a particular tool, implies there is a certain degree of difficulty and subtlety in the coding and construction of the runsets and also the mode of the PV tool, at runtime. [The complexity of this task is what is prompting the “unified  parser” methodology of TSMC’s iDRC program.  This is a vendor independent description language for the topological rules in the process.  At this time, the iDRC runsets do not provide for vendor optimized operation, and currently produce different results (number of real and false errors being flagged) from different tools when the results are compared in both flat and hierarchical modes.] This effort for the qualification of runsets, has led most EDA companies to run benchmarks for customers on their “preferred process” and existing designs, using “golden runsets” that are already qualified for the process, but area typically for other vendors tools.

When the runsets are used, the PV tools have a first step which is a parser that identifies where the input and output files are placed, which cell and level of hierarchy to start on, and verifies that commands in the runset have the right syntax and are interpretable by the core PV program.  It is in this step, that the vendors “run” each other’s files.  The results of the parser are a runset and associated files that guide the executable portion of the PV tool to do its job.  Lines of code in the runset that are not compatible with the PV tool are flagged with “warnings” and “non-fatal errors” and ignored at runtime.  In the “cross running” of runsets it is not unusual for a 2000 rule check file to have less than 750 “equivalent” checks that preformed in the other vendors tool.  The parser will also indicate issues such as which mode the tool is run in, and if associated support files are present.  In the absence of these files in the proper syntax/format, most of the PV tools default back to FLAT mode.  In flat mode, every polygon in the design is checked uniquely, rather then being checked inside of a cell so “2 input nand gate” is checked over and over for every instance, rather than being checked just once.  For a typical 65nm to 40nm design with 100M+ devices, it is guaranteed to crash any single CPU computer with up to 64G of memory, due to file size when checked in FLAT mode.

The parser also sets up the parallel processing and distributed computing modes for the PV tool.  As each vendors tool tends to launch differently and access the license server differently, when you run someone else’s runset, then the PV tools usually default back to a single machine (1 -2 CPU, and up to 8 cores/threads, license availability permiting) under an SMP environment.

When you compare the benchmarks or run runsets from one tool on another, you have make sure of the following:

(A) how many rules are being checked.

(B) if the parser and the warnings CHANGED any rules or options by substituting items that may change the context and intent of the rules.

( C) what mode the tool is running and on what cells the checks are being performed.

(D) what the IT infrastructure for the PV tools is set for when operated in recommended mode (how many CPUs, how much RAM, local or remote disk store, interactive or non-graphic display mode, licensing access and job submit methodology, etc)

(E) that the input file format is the same (launched from inside a tool on an internal database format vs from a GDSII or OA file)

(F) format and number of output files created.

These constitute the majority of the issues in comparing the runtime benchmark numbers between vendor tools.  The useful information for a design release is actually NOT the runtime numbers, as they tend to be less than 10% of the Physical Verification cycle.  The key issues on comparing the tools should be: (1) what is the signoff criteria from the FAB for release of a design to manufacturing – This is the main criteria, and (2) which has the most interpretable error flags for identifying not only what is wrong, but leads to how it should be fixed.

Having a tool that is fast at generating lots of flags, both REAL and FALSE and having to weed through them, is actually worse than a tool with 10% longer runtime, that has NO or MINIMUM False errors, and the context description of the rule so a fix can be determined.

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