Pallab’s Place

I recently had a chance to have a conversation with Judy Priest of Cisco about some of the design and packaging issues for accepting and qualifying new SOCs for high speed networking applications.  Historically, the high end network packages were being designed and selected as both heat spreaders and pitch spreaders between the IC pad pitch and those of the interconnect on the PCB.  This has changed in a current era of board level signals >20GHz and power supplies below 1V.

In order to meet these performance specifications, these networking systems have become very large die (around 20mm/side) and these are in packages occupying 55mm/side.  These can be either single die systems, multiple die arranged in a planar fashion in a single package cavity or thinned and stacked die in one package.  For single die systems, the package configuration has a great deal of influence on the placement and separation of voltage islands, and global placement of power down blocks and functions as dictated by the bond wire and board level signal integrity requirements. For multi-die systems, these same issues as well as data pattern based thermal management inside the package environment is also a key design element that needs to be fed back to the IC design as a floor plan constraint.  Stacked die (traditional, not TSV based) and very large single die have these same design constraints in addition to package and die / package warpage and material stress issues.  The warpage and stress that is in the package is variable based on the density and material used for the different styles of current generation HiK and Lead free packages.  These two effects can cause differences in the leakage power and timing  performance of the die since it mechanically changes the planarity of the silicon substrate.

Most high speed networking products are being deigned for 10yr+ die and package/bond reliability.  This brings back to the chip design and architecture level the final assembly criteria of die thickness, pad size and reliability for wire or bump bond, shock survivability from a drop test and wave solder/post assembly high temperature processing (a known susceptibility for technologies such as PCM memory).

Judy will be discussing these and more details about design tradeoffs between package and die at the MEPTEC Chip to System Symposium (http://www.meptec.org/meptecfromchipto.html) being held in San Jose at the end of February.  With the invasive nature of the need for high speed connectivity in most of today’s systems and SOCs, is driving package interaction from a niche issue to being a mainstream concern very quickly.

PC

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