Pallab’s Place

This week at the International Electron Device Meeting (IEDM), NEC presented their improved 40nm low power CMOS process that has been targeted at RF and mixed signal.  One of the major issues in addressing higher speed data communication for LTE, WiMAX mmwave and other protocols, is implementing analog transistors with high enough bandwidth to make functional amplifiers.  NEC has created a selective copper plug, called a Partially Thickened Local Interconnect (PTL) on the gates of devices.  This PTL interconnect reduces the resistance by 50% in the horizontal direction as well as a vertical resistance reduction.  (See figure 1 for cross sections of low-k process).

Figure 1 - PTL Cross Sections

The PTL interconnect does not impact the design rules of the process and can be implemented as needed.  As there is a increase in contact area, there is an associated increase in capacitance, which is proportionally less than the benefit of the resistance reduction.  As there is a capactiance increase, the PTL interconnect is being segregated to use only on gate electrode connections.  The use of the PTL interconnect allows for Fmax of the devices to be greater than 200GHz which enables data bandwidths up to 60GHz for fuctional RF front ends.

The process enhancement includes the ability to create these larger (non-uniform, non-minimum size) contacts simultaneously with standard contacts and NOT affect the process variability or component reliability.  This is accomplished with a Low O2 etch which slows down the etch rate for the larger openings and also does not impact the either the shot noise or the base thermal noise curves of the device.  The use of the PTL interconnect on the gate, results in a devices with a lower functional noise performance as the reduced resistance lowers the thermal noise of the device.  The experimental results have indicated that none of the device operation features are degraded with the additional of PTL.

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