Archive for December, 2009

Dec 16 2009

Chips on String by Jason Kim

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Question:  How would you insert 5 square millimeter chip through a needle?
Answer:  By stretching it into a thin string of 5 square millimeter chips.

Well, that is what I thought when I heard about SemiPack’s sub-micron multi-chip module assembly (www.semipack.com) at the BIOMEDevice conference held at San Jose Convention Center last week.  It appears that SemiPack has developed a manufacturing process to grind a wafer down to thin sheet and by slicing this thin sheet into thin strips, they can create a string of chips.  By applying this technique, they have recently developed 2 mm thin multi-layer silicon substrate for multi-chip module assembly for creating intravenous blood composition monitoring device.

Thus, it seems perceivable that we will be able to create active SOC laid out in a long strip to create monolithic BIOMED electronic string for minimally invasive and intravenous applications.  Perhaps, we may soon be able to attach MEMS flagella to make it propel along Intravenous network to monitor and supplement biological host system (http://www.ncbi.nlm.nih.gov/bookshelf/br.fcgi?book=mboc4&part=A2879&rendertype=figure&id=A2879).

This may sound far out science fiction, but this trend seems inevitable.   Dr. Deborah Schenberger explained during her presentation at the BIOMEDevice Forum that “Cardiovascular disease alone is claiming 850 thousand American lives each year.”  This is driving the frantic race for innovation on healthcare industry from medical diagnostic device companies to personalized genomic pharmaceutical companies.   For example, array of tiny needles on medical “Skin Patches” deliver slow-release medication through person’s skin (no more big scary syringes with long sharp needles) while Microfluidics could be placed deep within patient’s brain to allow precise delivery of designer drugs directly into their spinal cord.   It seemed, the whole industry is turning biological in this conference.

So, is this the beginning of the end for semiconductor industry yielding its ways to biological industry?  Not so, says the panelists of biomedical industry experts in Personalized Medicines.   Dr. Thomas Quertermous at Stanford University School of Medicine explains that the collaboration of multidisciplinary industry is more crucial now than ever for improving the efficiencies and efficacies of current healthcare industry for exponential growth and success it deserves.

Personalized medicine means massive information gathering to find customized solutions for each individuals in their own unique environments.   This requires all kinds of sensors and electronics – massive storage space for example to hold all these information captured from every facets of life.   And ultimately, it necessitates the need for even more computing power to efficiently sort through these massive data within acceptable time, space, and energy.   These calls for consolidation of all our engineering talents and scientific breakthroughs far beyond our current imagination.

Thus, it seems “Chips on String” would not be too far off from becoming the primary form of electronics.

Jason Kim.

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Dec 16 2009

Update on Magma Dec 2009

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Magma Design Automation is hanging in there as one of the big 4 public EDA vendors.  In a recent discussion with Bob Smith, VP of Marketing, who returned to Magma in March 2009 after a several year absence.  The discussion centered on a general update on where Magma is and what they are up to.
Mr. Smith’s marketing position is mostly focused on the digital products, so we did not have a discussion on the cell characterization tools or the analog products.  His understanding was that those areas were doing well based on customer feedback and benchmark data.
On the digital side, the first point that was made is that Magma is very busy on new technology having the tools be used for over 70 tapeouts at the 40nm node and they have a lot of activity at 28nm. In this definition, a tapeout is a design released from engineering to a fab. The tools are also still being used by customers at technologies back to 180nm, and in most application of really big designs.  These large designs (running with Talus Vortex v1.1) are typically 2M-3M instances that are being placed at the top level of the chip.  These large designs are typically flat (i.e. non-hierarchical) at the top level or they are flat “megacells” for use in other designs.
The other common trait of these designs is that they are low power designs which utilize multiple power rail pairs.  These multiple power rails can be automatically connected as separate voltage domains and support most of the low power methodologies including DVFS.  The Talus platform is also the only commercial package that is supporting BOTH UPF and CPF low power design methods.
There were two other points of benefit for the new platform – (1) it runs on a fairly minimum hardware platform – 4CPU, 32GB RAM, multi-threaded Linux (Red Hat / Ubuntu) and (2) the clock tree synthesis is now functional as a Multi-Mode Multi-Corner (MMMC) solution tool that can produce both flat and hierarchical clock trees to the Magma unified data model.  The direction for product improvement is on handling larger designs and additional variation for the MMMC analysis on the same minimum hardware configuration.  The target for all of these analysis is to maintain or improve the QOR for the designs.
On the topic of other products, their physical verification tool – Quartz, is now seeing use with a growing number of customers.  The big change in the product that prompted the increased use is the ability to natively read the SVRF rule file format used by the foundry supplied Calibre decks.  This eliminates the end user from having to translate and re-qualify the runsets for a given technology.
The financial position for Magma has been under discussion and rumor in the industry almost as much as the product direction.  Without going into all of the details, most of which are on the Magma web site with the transcript of the last quarter’s earnings call, Bob indicated they are doing OK.  They have had three consecutive quarter where they were cash positive at levels of single digit $M.  The concern during late summer was their structure for dealing with the bond that Is due in April of 2010.  Magma has successfully re-structured this note with over 50% now being deferred to 2014, and available funds or other payment structures for the balance.  The end result, is the April note is now a non-issue, and the company has an on-going positive cash flow.
PC

Magma Design Automation is hanging in there as one of the big 4 public EDA vendors.  In a recent discussion with Bob Smith, VP of Marketing, who returned to Magma in March 2009 after a several year absence.  The discussion centered on a general update on where Magma is and what they are up to.

Mr. Smith’s marketing position is mostly focused on the digital products, so we did not have a discussion on the cell characterization tools or the analog products.  His understanding was that those areas were doing well based on customer feedback and benchmark data.

On the digital side, the first point that was made is that Magma is very busy on new technology having the tools be used for over 70 tapeouts at the 40nm node and they have a lot of activity at 28nm. In this definition, a tapeout is a design released from engineering to a fab. The tools are also still being used by customers at technologies back to 180nm, and in most application of really big designs.  These large designs (running with Talus Vortex v1.1) are typically 2M-3M instances that are being placed at the top level of the chip.  These large designs are typically flat (i.e. non-hierarchical) at the top level or they are flat “megacells” for use in other designs.

The other common trait of these designs is that they are low power designs which utilize multiple power rail pairs.  These multiple power rails can be automatically connected as separate voltage domains and support most of the low power methodologies including DVFS.  The Talus platform is also the only commercial package that is supporting BOTH UPF and CPF low power design methods.

There were two other points of benefit for the new platform – (1) it runs on a fairly minimum hardware platform – 4CPU, 32GB RAM, multi-threaded Linux (Red Hat / Ubuntu) and (2) the clock tree synthesis is now functional as a Multi-Mode Multi-Corner (MMMC) solution tool that can produce both flat and hierarchical clock trees to the Magma unified data model.  The direction for product improvement is on handling larger designs and additional variation for the MMMC analysis on the same minimum hardware configuration.  The target for all of these analysis is to maintain or improve the QOR for the designs.

On the topic of other products, their physical verification tool – Quartz, is now seeing use with a growing number of customers.  The big change in the product that prompted the increased use is the ability to natively read the SVRF rule file format used by the foundry supplied Calibre decks.  This eliminates the end user from having to translate and re-qualify the runsets for a given technology.

The financial position for Magma has been under discussion and rumor in the industry almost as much as the product direction.  Without going into all of the details, most of which are on the Magma web site with the transcript of the last quarter’s earnings call, Bob indicated they are doing OK.  They have had three consecutive quarter where they were cash positive at levels of single digit $M.  The concern during late summer was their structure for dealing with the bond that Is due in April of 2010.  Magma has successfully re-structured this note with over 50% now being deferred to 2014, and available funds or other payment structures for the balance.  The end result, is the April note is now a non-issue, and the company has an on-going positive cash flow.

PC

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Dec 14 2009

IEDM 2009 – Numonyx advances phase-change memory

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At the 2009 International Electron Device Meeting (IEDM) Numonyx presented 4 papers about their advances in phase change memory based on their 45nm 4th generation test chip and process development.  These were in addition to the announcement that the 90nm 1GB PCM part was going to be available as a production product in Q1 of 2010.  This part has a pinout compatible with existing flash parts of the same configuration so it can fit in existing sockets.
The 45nm technology was selected for the 4th generation, continuing the technology node jumping that has been a hallmark of the PCM development since the 2003 JDP with Intel and ST, to get tot he goal of litho parity with DRAM and cell party with flash.  The new LP 45nm devices achieve a cell size of 5.5 feature sq, flash is at levels of 5 feature sq, and DRAM is at 6-8 feature sq.  The new 45nm product is targeted at enterprise class products and results showing reliability at those targets were achieved.  Results in tests based on direct bit addressing showed 1M cycles of write endurance, data retention over 10 yrs.  These are based on a 1.5v socket, where the lower power is achieved through zero (0) effective standby power and active power about the same as DRAM.
Additional papers covered the 3D aspects of PCM.  Papers were presented that had a thin film diode element for the select device in addition to the memory element, in a crosspoint array.  This would allow for veritical stacking of the memories which could reduce the effective cell area up to factors of 4 with a 5 layer stack.  The JDP with Intel has produced a 64MB device with multi-level PCM memories using both thin film (TF) select and memory devices.
The last paper presented the use of PCM in embedded applications. This utilized a standard CMOS select device with a PCM TFT memory element located over the active select device.  The memory core in instantiated as a standard macro block into a P&R flow and has normal keep-out and routing rules.  The major design consideration with the use of PCM in an embedded application, is the thermal properties of the memory element.  PCM memories are thermally programmed, as a result, any design with an embedded PCM memory will have to be after board assembly programed, as the solder reflow process (typically 130o ) will cause the memory to reset.
PC

At the 2009 International Electron Device Meeting (IEDM) Numonyx presented 4 papers about their advances in phase change memory based on their 45nm 4th generation test chip and process development.  These were in addition to the announcement that the 90nm 1GB PCM part was going to be available as a production product in Q1 of 2010.  This part has a pinout compatible with existing flash parts of the same configuration so it can fit in existing sockets.

The 45nm technology was selected for the 4th generation, continuing the technology node jumping that has been a hallmark of the PCM development since the 2003 JDP with Intel and ST, to get tot he goal of litho parity with DRAM and cell party with flash.  The new LP 45nm devices achieve a cell size of 5.5 feature sq, flash is at levels of 5 feature sq, and DRAM is at 6-8 feature sq.  The new 45nm product is targeted at enterprise class products and results showing reliability at those targets were achieved.  Results in tests based on direct bit addressing showed 1M cycles of write endurance, data retention over 10 yrs.  These are based on a 1.5v socket, where the lower power is achieved through zero (0) effective standby power and active power about the same as DRAM.

Additional papers covered the 3D aspects of PCM.  Papers were presented that had a thin film diode element for the select device in addition to the memory element, in a crosspoint array.  This would allow for veritical stacking of the memories which could reduce the effective cell area up to factors of 4 with a 5 layer stack.  The JDP with Intel has produced a 64MB device with multi-level PCM memories using both thin film (TF) select and memory devices.

The last paper presented the use of PCM in embedded applications. This utilized a standard CMOS select device with a PCM TFT memory element located over the active select device.  The memory core in instantiated as a standard macro block into a P&R flow and has normal keep-out and routing rules.  The major design consideration with the use of PCM in an embedded application, is the thermal properties of the memory element.  PCM memories are thermally programmed, as a result, any design with an embedded PCM memory will have to be after board assembly programed, as the solder reflow process (typically 130o ) will cause the memory to reset.

PC

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Dec 13 2009

IEDM 2009 – NEC improves copper contacts for RF

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This week at the International Electron Device Meeting (IEDM), NEC presented their improved 40nm low power CMOS process that has been targeted at RF and mixed signal.  One of the major issues in addressing higher speed data communication for LTE, WiMAX mmwave and other protocols, is implementing analog transistors with high enough bandwidth to make functional amplifiers.  NEC has created a selective copper plug, called a Partially Thickened Local Interconnect (PTL) on the gates of devices.  This PTL interconnect reduces the resistance by 50% in the horizontal direction as well as a vertical resistance reduction.  (See figure 1 for cross sections of low-k process).
The PTL interconnect does not impact the design rules of the process and can be implemented as needed.  As there is a increase in contact area, there is an associated increase in capacitance, which is proportionally less than the benefit of the resistance reduction.  As there is a capactiance increase, the PTL interconnect is being segregated to use only on gate electrode connections.  The use of the PTL interconnect allows for Fmax of the devices to be greater than 200GHz which enables data bandwidths up to 60GHz for fuctional RF front ends.
The process enhancement includes the ability to create these larger (non-uniform, non-minimum size) contacts simultaneously with standard contacts and NOT affect the process variability or component reliability.  This is accomplished with a Low O2 etch which slows down the etch rate for the larger openings and also does not impact the either the shot noise or the base thermal noise curves of the device.  The use of the PTL interconnect on the gate, results in a devices with a lower functional noise performance as the reduced resistance lowers the thermal noise of the device.  The experimental results have indicated that none of the device operation features are degraded with the additional of PTL.
PC

This week at the International Electron Device Meeting (IEDM), NEC presented their improved 40nm low power CMOS process that has been targeted at RF and mixed signal.  One of the major issues in addressing higher speed data communication for LTE, WiMAX mmwave and other protocols, is implementing analog transistors with high enough bandwidth to make functional amplifiers.  NEC has created a selective copper plug, called a Partially Thickened Local Interconnect (PTL) on the gates of devices.  This PTL interconnect reduces the resistance by 50% in the horizontal direction as well as a vertical resistance reduction.  (See figure 1 for cross sections of low-k process).

Figure 1 - PTL Cross Sections

Figure 1 - PTL Cross Sections

The PTL interconnect does not impact the design rules of the process and can be implemented as needed.  As there is a increase in contact area, there is an associated increase in capacitance, which is proportionally less than the benefit of the resistance reduction.  As there is a capactiance increase, the PTL interconnect is being segregated to use only on gate electrode connections.  The use of the PTL interconnect allows for Fmax of the devices to be greater than 200GHz which enables data bandwidths up to 60GHz for fuctional RF front ends.

The process enhancement includes the ability to create these larger (non-uniform, non-minimum size) contacts simultaneously with standard contacts and NOT affect the process variability or component reliability.  This is accomplished with a Low O2 etch which slows down the etch rate for the larger openings and also does not impact the either the shot noise or the base thermal noise curves of the device.  The use of the PTL interconnect on the gate, results in a devices with a lower functional noise performance as the reduced resistance lowers the thermal noise of the device.  The experimental results have indicated that none of the device operation features are degraded with the additional of PTL.

PC

One response so far