Archive for May, 2009

May 21 2009

Silicon FrontLine – Field solver accuracy in a production RC tool

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Two of the founding members of Nassda Corporation have started a new EDA firm focused on post layout RC extraction.  The new firm Silicon FrontLine was formed in 2005 and formally funded in 2007.  The company is introducing two products F3D which is a Field Solver based RC extraction tool and R3D which is an On-Resistance modeling tool for power devices.

The F3D tool is targeted at “guaranteed accuracy” under the assumptions that if the correct process technology is input, then the results coming from a full field solver should be the “correct” answer.    The core of the Silicon FrontLine technology is on the rapid solution of the field solver and the identification of the conditions and situations to which the solver is applied.  The solver is multi-processor, multi-core and distributed aware, so high throughput is possible with most compute server environments.

As a result, the product can be integrated into standard physical verifications flows from Mentor, Synopsys, and Cadence.  The flows can use either flat or hierarchical design methods, and verification flows, the results come out as a flat netlist.  The F3D tool produces RC netlists and the R3D product produces detailed resistive structures for power devices and large drive transistors.  The integration with the standard flows provides the option of either letting the standard PV tool identify and extract the devices, and leave the interconnect for the F3D and R3D tools or re-code the device recognition for the SiliconFrontline tools and have it identify both the devices and the interconnect.

The current release of the toolset is available for the Linux platform and supports its own technology file format, standard GDSII data input, and outputs SPICE.    The mesh structure of the tool allows it to target advanced applications such as image sensors, data converters, non-uniform current flow, and complex post layout mfg effects such as CMP and metal fill.

For advanced process nodes (e.g. 40nm) the tool has been correlated with both measured and simulated results, and shows single digit percentages of discrepancy in a large number of cases.
Information on the products can be found at


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May 11 2009

Synopsys ICValidator – Next Generation PV

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Synopsys has finally released the long awaited next generation physical verification product to Hercules to address ultra sub-wavelength (45nm and below) process technologies.  The new product is called ICValidator and works as an add-on/integrated product to the ICCompiler product.  There are three (3) areas of major overhaul and change over prior products: (1) The product is natively written to support multi-core, multi-processor and distributed environments, (2) there is a new programming and control language (PXL) and (3) the complete re-architecting of the product to support both polygon AND edge based verification and logical operations and objects.  The change to support both polygon and edge based verification now allows for high throughput of gridless processing of both design data and blockage data.

The updating of the code base from a single core, single process task to a multi-core engine, has several impacts.  Not only is the design data segmented into multiple machines and processors cores but the runset is also distributed.  The new parser can split the runset to work on separate processors although, the algorithm for doing this was not discussed, the Synopsys staff indicated that the multi-generational historic issues of hierarchical data and flat data in combination with common sizing and spacing rules no longer is a problem for the runset splitter which supposedly now results in near linear scalability with processor count.

The ICValidator product is a supplemental licence to existing Hercules licenses for most users who are migrating to the new processes.  The staffing requirement is that the same personnel would be able to support both programming languages as the new PXL language is easier to use, smaller and more compatible with object oriented construction as the other Synopsys programing languages are.  There are training and transition programs being put in place at Synopsys and new runsets should be available from the foundries.

The ICValidator product is designed for use in an interactive flow that is closly tied with the ICCompiler product.  The concept is to create a closed loop “single pass” between the design creation and actual clean design closure.  The loop includes timing aware routing, timing aware ripup-and re-route for drc repair (i.e. fixing PV errors automatically including multi layer edits), full custom editing modifications both manual and automated, PV and DFM as required.  The new flow is targeting the loop happening at the design creation stage of each design module as it is initially created, this making a “correct by construction’ block, and having just a final assembly level “sanity check”, rather than the traditional, complete a full design and then do full hierarchical PV and have to perform, correct and re-validate the entire design due to corrections.  The correction methodology is such that for sub 45nm processes, it is preferred to leave out complex routing constraints such as corner rules from the router, and then have the PV tool flag and repair the error in a smaller area.

The idea to integrate the ICValidator product with ICC as a combined flow tool is interesting.  Either they have new EDA marketing people who do no know past campaigns, the memories are short at Synopsys, they believe the memory of their customers is short, or their optimism is higher for the re-use of the tag line “single pass” from the old Avant! Aquarius and Vericheck flow. The marketing concept is good of a one step solution, however the execution of the old “single pass flow” typically did not come out shorter than mid 2 digits worth of spins per blocks (as compared to 3 digits of spins per blocks with other tool flows) for real chips besides the powerpoint benchmark chip.  This flow with the ICC integration, PV& DFM and autofix seems targeted towards the same fate.

Synopsys is known for bringing out strong technology products that actually perform well in real applications, for real engineers, and making sure they are stable when they are released.  It looks like this is just such a product and in reality will be strongly embraced by both the foundry and the design communities.

It would be beneficial to these communities if the marketing information associated with the products were directed toward real features of the product and how they apply to actual design data (about 20% of the current pitch info) instead hype that is re-tread from the Avant! flow slicks cira 1990′s.


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May 08 2009

Gennum at NAB 2009 – Filling the floor 3Gb/s SDI

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The past few years have seen the video broadcast industry dealing with a creeping need for bandwidth and throughput.  This was also met with a trend toward the use of IP blocks in SOCs to address some of the many different avenues of the broadcast marketplace.  The key pieces going into these SOCs the past couple of years has been the SDI interface blocks and the different types of video protocol converters (JPG2000, MPEG4, etc).  The majority of these designs were being implemented in FPGAs.  However, as the transition to digital broadcast becomes immanent, more studios and stations have opted for more traditional high performance specific task hardware that is optimized for the specific broadcast functions.

Gennum has addressed this need for high performance standard products with a group a 10 new 10Gb/s SDI chips that were introduced in April 2009 and demonstrated at NAB.   Gennum initially was a small mixed signal semicoductor company focusing on video, data converters, hearing aids, and custom mixed signal.  They have now rel-aligned and re-targeted on the markets on Video Broadcast, Data Communication, A/V Connectivity and IP Core Licensing.  The current corporation is operating at a 2008 revenue of ~$127M USD and 76% gross margins.

Using these resources, their R&D was able to deliver the following products which may be available as IP cores in the future. One is a3GB/s receiver with equalizer that can drive 160 meters of coax cable.a 3GB/s video optical receiver module that is “error free” over a 60km link, capture solutions using new PCIe bridge and PCIe extender products, and finally a new class of power efficient equalizers, reclockers, and cable drivers.  These products are all either sampling or available in 2009.


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