Archive for April, 2009

Apr 22 2009

Cadence Implementation Products Group – Q2 ‘09

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Dr. Chi-Ping Hsu is the Sr. VP of R&D of the Implementation Products Group at Cadence.  Dr. Hsu come to this position at Cadence from key technology leadership positions at Get2Chip and Avanti.  Under the current version of organization, this group is responsible for several product areas – CIC: Virtuoso and other custom physical design tools, CSV: Simulators and DFM/Litho products, ICD: Place & Route / Signal Integrity / Timing, and SPB: PCB / SIP and Packaging.  The group is also responsible for several industry initiatives – the long standing Open Access (OA) database initiative, the Power Forward Initiative and the new Mixed Signal Initiative.

The reorganization is centered around the strength of the new anchor products.  The feature sets in IC 6.1.3 that are part of the open access versions of Virtuosos and EDI (Encounter Digital).   These tools while incompatible with prior design data from version 5.1.41, has been receiving strong responses from customers who have chosen to recreate designs from the ground up in the new tools and simulate them with the new simulator.

The new environment also hosts a new line of multi-threaded and multi-core aware simulators that are a departure from their traditional single core products.  These multi-core products provided increased throughput of 12-20x over the single threaded products.

The current flagship of the new product is the low power solutions under the common power format.  The low power solutions both in products and services are an integral portion of the revised Cadence design platform.  It is addressing the advanced process marketplace in the low power SOC application space that does not rely on legacy data, so entry into the new tools and new simulators is not an issue.  The use of the new tools results in the use of new flows and new services and support infrastructure.  On this basis, Cadence sees a strong business case for those that choose to adopt the IC6.1.3 platform or the Low Power Solution/CPF format.

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Apr 21 2009

Lenovo Hardware Password Manager

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Todays PC systems are protected by 4 basic hardware passwords a user and an admin password for accessing the motherboard and a user and an admin password for accessing the harddisk.  In most enterprise environments, these passwords are not used, due to the difficulty in administrating them.  As a result, most data is not is not fully secure in design and compute environment.

Lenovo started 4 years ago to address this issue by implementing a bios level solution to the problem.  They have just released their hardware password manager that introduced an IP telecom stack into their BIOS. This is a custom modification of the standard Phoenix BIOS that has been provided with their Thinkpad products.   Unlike the Intel Vpro solution, this is not a chipset or cpu specific solution, it will eventually support all of their platforms.

Providing these functions to IT administrators so they can  remotely manage employee hard drive passwords, including drives that are self-encrypting, the new tool can help companies reduce the time and expense associated with recovering and resetting employee passwords.  The BIOS level hardware password manager allows a standard wired network connection to be used to verify, change and support the motherboard and harddisk passwords.

This methodology supports all brands of FDE (Full Disk Encryption) self encrypting drives. The password control works for both local drives and any network attached drives that released at the time the passwords are cleared.  This password control also works with fingerprint scanner authentication.  The password control for the motherboard controls the powerup control and provides a “ConstantSecure” Remote Disable function which allows a user to remotely disable a machine if lost or stolen the next time it is connected to the internet or attempted to be powered up.

Lenovo Hardware Password Manager will be available worldwide starting in early May.   A video link of the product at work can be found at YouTube at:  Lenovo Hardware Password Manager

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Apr 09 2009

ebeam initiative – a mfg solution that starts with a design flow

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A new industry initiative (www.ebeam.org) has been brought to the design marketplace focusing on a cost effective solution to the low/mid volume and prototype requirements on cutting edge deep sub-wavelength processes (90nm and below).  The managing sponser company D2S, Inc has brought together a strong initial partner/member base, a strong leadership group, and a very directly focused goal for the group.  Aki Fujimura (EDA veteran most recently from C-Level positions at Cadence and Simplex Solutions) has organized a group with the simple focus of creating a design and supply chain for prototype manufacturing without masks that starts with optimized design data and software, and goes through a modified data fracture environment to direct write of wafer via e-beam on new optimized fabrication equipment.

Based on the directed focus of the initiative, the dramatically increased cost of masking and fabrication of sub 90nm processes, and the current world economic situation, all aspects of the design flow have chosen to participate from the initial stages.  These partners can all be found at http://www.ebeam.org/members.  The group has already started a 65nm prototype as proof of concept on the flow back in Oct 2008, and the run is a collaborative effort of the partners D2S, eSilicon and Fujitsu.

A change in this design solution, is rather than being an after-the-fact DFM correction flow, the design starts with IP that is optimized for the fracture routines and the design patterning optimization of the direct write e-beam equipment.  As such, the level of optimization sought and can potentially be provided is well beyond that of any single point in the flow optimization solution.  Several differentiating aspects from other “DFM like” programs is the inclusion of members such as Tela Innovations and Altos Design, which are in place to validate the usability of the design IP for both the customers and in real tool applications.

To help bring structure and organization to the initiative, they have enlisted the services of another multi-disciplinary veteran, Jan Willis, as the initiative facilitator.  Jan is well known form her work at Cadence on the industrial relations/partnering side and as facilitator for the the X-Initiative.

The program is targeting an anticipated design throughput by the end of 2009, of 1 direct write wafer/hour using the proper design libraries, VSB (variable shaped beam) fracture and CP (character projection) fracture on the newly design equipment and flow.  This is definitely a program to keep track of, as the solution can mean high 6 figures/low 7 figures of cost savings per design using a direct write methodology over a masking and MPW prototype flow.

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Apr 09 2009

MUSIC Silicon Valley April 2, 2009 – by Jens Andersen

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Opening Address by MUSIC Chairman Dr. Uming Ko, senior fellow and director of the Worldwide Chip Technology Center from Texas Instruments. 150 attendees were registered and the opening address had one third of them. Dr. Ko opened MUSIC on a positive note looking at the new problems we face in the industry including the economical downturn as challenges. Point being the feature sizes keeps reducing further and all the devises that we use must have portability, ability and capability. The challenge today is the batteries ability to power the devices.

I drifted between the various sessions by Magma and customers: TI, nVIDIA, IDT… The excitement at the user conference were lingering in the sessions, initially covering Titan’s ability and Talus’ speed improvements in the Analog Design and Circuit Simulation covering highly intensive migration across Analog and Digital domains, through Magma’s new approach to mixed signal portability that is being developed as I write.

I ran into Magma Chairman and CEO Rajeev Madhavan in the hallway who was bubbling of excitement that one usually sees when companies back in the late nineties were about to be acquired. However, his excitement was, at the show, about being able to migrate mixed signal designs both logic and analog, from process node to process node once the designs were in the Magma systems, the announcement will be announced at DAC in San Francisco in July. Rajeev also mentioned how they have been able to reduce Talus’ runtime by 3X and expects to see further reductions by September of another 2X.

Rajeev’s excitement carried into the Keynote where all the 150 attendees patiently waited. Rajeev started with a quick look at the economy which along with many other things has forced Magma to do things differently and go “back to basics” (haven’t we all been forced to that lately), and focus on the core values. Magma can’t succeed alone on “me too” solutions unless one can show a 10x speed improvement, and thus Magma’s new breakthrough with analog migration. So what’s next: Last year Magma’s focus was productivity for SOC designs and they claim the ability to handle up towards 100M cells in the next 6 months by parallel distribution of the various blocks. In addition, the support burden has been reduced along the runtimes. However, the excitement that was left hanging after the keynote, was the announcement of Titan’s ability to, once design has been captured, with some work in capturing it initially, move the designs from process node to process node, enabling one environment for analog and digital designs = TITAN.

We have been facing the same “me too” issues at Nangate until we enabled application specific library development capabilities. DIFFERENTIATION IS KEY IN THIS ECONOMY!

Jens C. Andersen, Special Topic Editor for Extension Media, and VP of Worldwide sales and Managing Director of US Operations for Nangate Inc. Nangate develops tools to create standard cell libraries, and optimization tools and services enabling application specific libraries resulting in optimized speed, area and power. jca@nangate.com

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