Archive for February, 2009

Feb 27 2009

IMEC platform designs at ISSCC ‘09

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At the 2009 Solid State Circuit Conference IMEC (Belgium) had a number of presentation on their advanced CMOS design development.  A number of the papers were on single chip implementations of telcom products (e.g. 60GHz CMOS receiver chip).  There were two papers presented which provided a peak into the new system platform products that should be appearing in industry soon.  These were the software defined radio front end and the integrated capacitive power management circuit for thermal harvesters.

The software defined front end is a monolithic 45nm CMOS design that includes a new “digital RF” signal path.  The front end is a platform design that utilizes a single chip that contains both a receiver and frequency synthesizer that can address multiple radio formats includeing DVBH and GSM.  The design has selectable channel bandwidth from 0.2-40mHz and support RF frequencies from 0.1GHz-6GHz.  This front end addresses multiple applications with a flexible power/performance capability and a 1.1v operating voltage.

This implementation supports a different architecture from other software defined radios (e.g. IP available from Imagination Technology and others). The new scheme requires a high speed, high resolution ADC (target 10 bits at 100MS/s) and places the ADC circuitry direction after the LNA.  This results in directio RF digitization with a continuous time BPF as part of an RF Bandpass Sigma Delta converter.  This is the second generation all CMOS implementation following on from Nov 2007 work on a 6.3bit 60MHz design (2.4GHz freq band @ 3GHz clock) that was built in 90nm CMOS.  The goal is to allow for a multi-application platform can deliver a power/performance solution to provide the high volume production that can justify the high cost of the process technology selection.  The design parameters associated with the creation of this high performance analog product are a result of the advnaced development in process technology and lithography that is simultaneously on-going at IMEC.

The power mangement circuit is a key piece for the generation of as needed on-body and in-application industrial sensors.  Most of these circuits suffer from low conversion efficiency and a large amount of relative operating power for the power output made available.  This circuit, implemented in a low cost medical aware 0.35um CMOS process, incorporated a charge pump and a full DC-DC converter for power regulation.  This module is the core of future work being done on medical and industrial sensor applications, that need remote power.  The design is scalable, by adjusting the number of stages used, to create difference power supplies for different applications.  Once again, this is a general purprose platform product that is addressing the “autonomous” sensor application space by utilizing only 1uA of control current and resulting in a 70% overall efficiency of the TEG and regulator design.

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Feb 19 2009

It’s Time For EDA To Evolve

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The EDA industry’s hard times are tied directly to the changes under way in the semiconductor and electronics industries.

The semiconductor and electronics industries are shifting their designs and their business models to better address the current market conditions. These shifts are happening in two directions. One is toward smaller, specific-function analog/ telcomm/ datacomm/ sensor chips. The other is toward platform SoCs that are software-programmable.

And behind both of these shifts is another major change, which is the globalization of the supply chain and supply-chain management. Historically, system products (transportation, white goods, consumer electronics, industrial telecom/datacomm, avionics, etc.) were differentiated by their components and performance.

The advancement and adoption of Moore’s law and the capabilities provided by the increasing device count has predominantly rendered component count in digital circuits meaningless. The functionality that is provided is now the key. The “gates per design” metric is gone. So are the performance metrics, because most major function blocks have “standards” of performance rather than minimum limits of performance.

This new paradigm for electronic product development is central to customer product lifecycle management. It requires a design automation flow that includes concept capture, component selection and design capture, board- and assembly-level design capture, industrial and mechanical design capture. And this flow needs to be aware of the manufacturing process control and customer management. These design capture tools include capabilities for hardware, software, and firmware development, in addition to sheet metal, plastic, display, input devices and power source design. The design management has been an overall flow that incorporated all aspects of the supply chain since early electronic design—even in the pre-tube era.

EDA had emerged as a technology focusing on component hardware development. It was introduced as a business model that was a parallel track to the rest of the design cycle. The motivation for the parallel nature was to support a faster and more innovative path, which was in sync with the advancing process technologies, while the rest of the design chain advanced at a more normal pace. During this period of time (approximately from the 1970s through the early part of this decade), component-level semiconductor design was dealing with a large, diverse client base building many types of custom circuits on rapidly changing technologies. This resulted in semiconductor-specific EDA being focused on supporting an industry out of context with the rest of the supply chain.

Today’s cost of manufacturing on state-of-the-art processes has significantly reduced the number of clients in the “bleeding-edge component-only” development space. The majority of designs on current process technologies are large systems-on-a-chip that are supported by software, firmware, embedded test, key external components, and are not targeted to single function activities. These designs require complete supply chains and lifecycle tracking to support the component-level development process.

These trends on the requirements of system-level design and the manufacturing aspects of component development have been injected into the EDA space under the titles ESL and DFM. The incorporation of information through available design conduits and the adopotion of new EDA methodologies to use this information have been both costly and time consuming. A more practical approach than exporting the continuous supply chain information to the EDA tools is to have EDA be re-folded into the design chain as generalized design automation. This is progressing with several of the EDA vendors with their expansion from core calculation-based engines to include IP, firmware and software development, component to board modeling and evaluation and simulation/modeling of manufacturing/process development.

There has been discussion as to whether or not EDA is alive or dead. From a practical standpoint, the necessity of tools and solutions exists and will continue to exist. The innovation of the community is still strong and will continue to exist and the growth and development of the electronics industry will continue to exist.

However, the separatist nature of the EDA business model and its associated elitist pricing/licensing model no longer can be supported by the integrated global economy and the distributed supply chain. The survival of the semiconductor and component-specific design automation technology associated with EDA is inevitable. The business of EDA as a standalone sector is near the end of its predicted and expected life span.

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Feb 10 2009

Cadence Bldg 10 San Jose – New R&D Center

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Cadence had an official open house on their new R&D Center in San Jose.  It was an event attended by many Cadence employees, group directors, board members, the architects, city council members and the Mayor of San Jose.

The building is a single 5 story structure that will house a combined R&D group from the many divisions of Cadence in one central location and support for full video conferencing to their remote location development centers.  The building is a very open and peaceful environment with outside spaces that is designed to promote “open thinking” and “foster new ideas” for the company.  In addition to the open layout of the building, there is a new high profile, state of the art auditorium that will enhance the ability for them to provide internal and external technical presentations.

Several of the key Cadence executives who spoke talked of the increase in productivity that will be provided by this new facility and that this should help return Cadence to its leading position in EDA faster than most people think. Also appearing, but not speaking were Cadence Board Members Dr. Alberto Sangiovanni-Vincentelli and Don Lucas as well as new CTO Charlie Huang.

The opening of the building in a short two years since the groundbreaking, especially with such an innovative architectural design, is a very impressive accomplishment.  The big question is: Will the new management allocate the same sort of resources and implementation efforts to their product line for support of existing and development of new products.

Video and photographs of the ribbon cutting ceremony can be seen at the Cadence newsroom website soon.

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Feb 10 2009

ISSCC – Classic Analog Mistakes to Avoid – evening session

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There was a panel discussion that had six members with illustrious histories in analog design. The panelists included Bob Blauschild, Paul Brokaw, Jim Williams, Klaas Bult, Kofi Makinwa and Zhiliang Hong. The topic of discussion was basically here are things we have encountered that appear to be correct, but actually do not work and why.. They showed some of the historically common errors that have occurred and still occur in analog design.

The examples of mistakes made included:
*    the swing and frequency dependance of a gate capacitance being used as compensation for amplifiers,
*    making everything in the design programmable such as bias current and gain and then implementing the controls that requires that control data be loaded into the circuit prior the circuit being functional.
*    ground, ground loops and metal resistance causing unpredictable performance that was not identified in simulation
*    simulation and verification of the with out startup circuitry.

Jim Williams passed on several words of wisdom that are traps for the mindset behind good design engineering.  These words of wisdom were:
*    Avoid falling in love with the way you solve a problem and the associated avoid falling in love with an explanation for observed phenomena. when you always rely on a solution that has worked in the past, then you stop being innovative.
*    The biggest danger is following the idea of  “its done and it works”.  The design should be never be thought of as done nor should it be thought of as good enough.
*    The last dangerous idea was “it is just a tweak or this will make it better” these are concepts which lead to unnecessary risk in completing design.

The panel was very well attended (80% of the seats available – excellent for an evening session), quite well received by the audience and included questions, examples (on an overhead projector and with foils & pens), and comments on other common analog problems by the audience.

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Feb 03 2009

Xilinx Vertex 6 and Spartan 6 platform FPGAs

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Xilinx introduced two new FPGA product families which are platform based for communication targeted applications.  Traditionally the FPGA families have been based on a technology node and maximizing an I/O count and core cell density.  The new products are split over two process nodes 45nm and 40nm.

The initial reaction to the split technology node on a new product family is that there will be inherent incompatibilities in designs created for the smaller capacity products vs the larger.  The products are targeted for standard function applications such as high speed serial data communication, display accelerators, device communications (e.g. SATA) and programmable DSP blocks.  These blocks are defined by an interface / functional specification NOT a technology / performance specfication.  The target of the new product line is to provide a single die solution for full systems that include video, processors, memory and high speed Interfaces.

The product line consists of 5 members which range from simple logic with a DSP core to ultra high speed logic with large DSP cores, serial and parallel connectivity and memory.  The Virtex 6 family is supported by a software platform, reference board designs, development board systems, and a large functional IP library.  The new products are targeted toward automotive infotainment systems, low power wired and wireless communication systems, flat panel display systems and other currently “multi-component” high speed data systems.

This product announcement follows the recent re-introduction of the Virtex 3 products and development environemnt for the automotive marketplace.  The Virtex 6 product line is the first FPGA product that has shifted it focus from “speed of the datapath” to “architecture to address an application”.  The low power handling and large design margins available for standard data processing will make the FPGAs a very viable alternative to a multi-die / multi-component board solution.

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