Pallab’s Place

The IEEE’s Electron Device conference has traditionally focused on advancements in process technology, new devices and the modeling and understanding of how these devices and the process chemistry/physics works. The conference has been and continues to be the main stage for the announcement of new and novel devices, new process migrations, and new analysis techniques to being able to monitor these devices and prepare them for volume manufacturing. Registration and attendance was high in the context of the current economy and industry environment.

The conference has not been a strong hold of circuit design and system application information, except for memory technologies, as that has been covered by other IEEE societies and events. This year’s conference has shifted this trend and full acknowledged the tight coupling of generalized design tradeoffs and process technology for DSM and Nanoscale processes. The conference featured several keynotes on this topic as well as several full sessions. The sessions included: Nanotechnologies for Medicine and Biology, Biosensors and 3D Hetero Integration, and Issues at the Confluence of Technology and Design.

The Medicine and Bio sessions presented information that was very representative of the direction and challenges in this area. With an audience comprised of both design engineers and process technologists, aspects of bringing bio products to production ranged from:
- system segmentation (internal, and external partitioning of hardware, software & UI control)
- system packaging and interconnect technology for multi-chip systems – flexible vs traditionally rigid structures
- Power and temperature constraints – most electronics utilize external power that is replaceable and power issues are bsed on extending battery life. In the Bio interface designs, operating temperature changes in excess of 0.1C are a problem for implantable devices as well as the requirement for passive power coupling to avoid repeated invasive procedures for battery replacement.
- drug delivery options that take advantage of MEMS and Nanowire technologies. These papers presented how to use standard, proven, electronic MEMS processing or Nanowire growth on spheres to create solution options for directed point of treatment. The MEMS product was a series of electronicly controlled reservoir chambers that could programmed for release on a fixed long term program basis. The other paper described standard nanowire creation to make absorption optimized drug delivery spheres.

The Biosensor papers were very circuit and design oriented rather than process technology oriented. There was nice background to the attending audience for the DNA sensitive FETs and the modeling behavior that goes with the design. This session also covered nanowire sensors and 3D assembly techniques including TSVs (Thru Silicon Vias). These assembly techniques and sensor materials are new applications of process technology that was nominally targeted towards multi-chip high density memories.

One of the larger sessions at the conference consisted of ONLY invited papers and focused on Issues at the Confluence of Technology and Design. The first talk , by Professor T. Sakurai from the University of Tokyo focused on technology behind low power design methods, those that are circuit derived and those that are process derived and their impact on potential yield and manufacturability. The premise being only small portions of the design are performance critical while all devices present in the design are power critical.. The second talk, by Professor P. Gupta from UCLA will discuss the use of devices with tunable parameters that can be implemented late in design cycle. The key is to allow for tunability, not redesign, that will help meet production requirements without the need for a full re-characterization cycle. The techniques reviewed included some that are already part of OPC and post processing capability but not part of any standardized flows. The third talk, by Professor A. Strojwas from Carnegie-Mellon University and PDF Solutions, was somewhat contrary to the the second paper, in that it adovcated reduced design rules and as the method for tradeoffs between yield, variability, and robust design. The fourth talk, by Professor A. Asenov from the University of Glasgow, addressed the exponentially increasing area of analysis of variability and its impact on design using statistical simulation techniques to model variability and reliability in highly scaled devices. The last three talks addressed specific application areas and technologies. These talks were by Professor D. Sylvester from the University of Michigan on the design of robust low-power circuits; by Professor K. Makinwa from TU Delft on CMOS temperature sensors; and by Professor M. Horowitz, from Stanford University will focus on the requirements for future devices intended as CMOS replacements.

pc

Samsung recently held thier annual technology forum and analysts event.  The discussions covered the topics of Digitial TV, LCD panels, Mobile Communication systems divisions as well as the Memory and System LSI component divisions.

The memory division separated their discussion into the areas of DRAM and Flash.  Due to the worldwide economic conditions, both of these divisions showed weaker performance than expected, however they are both targeted to finish the year in a stronger position than thier competitors in these marketplaces.

Currently, Samsung DRAM technology is using a 56nm process line rampup., Due to severe price erosion in the marketplace and a drop in market demand, has an end retail price very close to the manufacturing costs.  In response to this situation, Samsung is planning to dial back the schedule on the production ramp for DRAM.  The DRAM process migration is moving to the 4xnm and 3xnm modes to address the DDR3 products.

Thier NAND market situation is very similar to that of DRAM.  They currently have a rampup in progress on the 42nm node and the goal is to produce products in sync with the industry embracing   SSD technology to utilize the NAND Flash product.  Thei SSD (Solid State Device) market is a driver forthe 2009-2011 market.  In order to address current market positions, Samsung will be cutting back some of thier 8″ NAND capacity.

In addition to the standard memory products, they have been enhancing thier multi-chip module capability.  Thier newest designs use TSV (Thru Silicon Vias) have been tested using a 32 chip high stack.  Most of their MCP stacked products are 9 chips high, 8 memories and a control interface.  These will be used in the DTV, Mobile handset and SSD market applications.

The NAND products for SSD applications are targeting the 42nm process for ‘08 and shifting to 3xnm nodes for ‘09.  This will address the ‘08 products using the SATA2 (3GB datarate) spec and the ‘09 products using the SATA3 (6GB datarate) spec.  The NAND products are moving from a CE based application to include an embedded application base.

To simplify application in the embedded space, Samsung has introduced the OneNAND product.  This is a multi-core product that contains traditional NAND high capacity cores a;song with high speed SRAMs and a NOR logic interface with ECC logic.  Although the OneNAND product was introduced in 2003, they are now in volume production on the 51nm node at 1, 2 and 4Gb capacity and at 42nm node for the 8 Gb product.  These products can currently be found in thier higher end mobile phone products.

The architecture and and business model for the OneNAND product line has been adapted for the introduction of the OneDRAM product line.  The conventional solution for mobile video requires two (2) RAMS.  The OneDRAM product allows a single memory to meet the requirements of botht he baseband and application CPUs which can result in a significant performance increase over standard 2 memory configurations.

The LSI division has migrated from internal use function specific component solutions to full SOC platform solutions.  These include leveraging their low power process technology, CPUs, advanced IP and memory solutions with assembly into Mobile SOC soltions and system level optimization including UI and software development.  Some of the key points of this offering are the jointly developed Samsung/IBM 32nm HKMG (High K , Metal Gate) process technology which is offering a ver low power high performance option and the POP (package on package) solution incorporating OneDRAM technology.  The POP solution allows for the stacking of an application processor and a NAND/DRAM MCP in a single 16mm form factor package.  This reduces I/O through the use of high speed serial interface vs traditional parallel interfaces, increased performance, reduces EMI and meets the form factor of the end application such as mobile communication or image capture products.

One of the last areas of discussions was the digital imaging and mobile camera productsproducts.  Following prior attemts by Samsung and other companies, they have reduced the pixel size to target higher resolutions and are attempting to address the depth of focus and brightness issues using backside illumination.  This may result in an increased sensitivity of the design, but has historically resulted in a yield and quality reduction that offset the benefit of the sensitivity increase.  It remains to be seen how thie attempt works towards developing auto-focus, extended depth of field camera phone products greated than 5MP in resolution.

PC

Adobe Design Systems held thier annual MAX event in San Francisco in Nov.  The event was split fairly evenly on still image/document creation and moving image (video and MID content) creation.  One of the high points was the use of multi-processing and hardware acceleration on the current releases of the design software.

The Adobe CS3 product has been optimized for the the multi-core Intel processor architectures at the 65nm & 45nm nodes (Penryn microarchitecture).  The product is now multi-threaded and multi-core aware for the After Effects module and most of the rendering tools.  The tool set was created using the Intel developer tools including Intel Vtune Performance Analyzer, Intel Thread Profiler, Intel Integrated Performance Primitives and the Intel C++ Compiler.  These tools allowed Adobe to address and optimize use of the 47 commands from the Streaming SIMD Extensions (SSE4).  Under the Windows XP 64 bit OS, the results of these optimization methods and the advanced processor support, allows performance such as a real time cross dissolve of two (2) HD (720p) MPEG video streams using Adobe Premier.

The CS4 products and many associated add-ons (e.g. GridIron Software’s Nucleo Pro 2) are continuing this multi-core optimization.  This multi-core & multi-threaded support represents pretty much a wholesale rewrite of the main code blocks of the program.  The performance enhancements and new capabilities possible with the product appear to have produced a payoff that justifies the risk of the code re-write.  This trend is continuing with the add-on products to the CS3 and CS4 family.

One of the other acceleration options that was presented was the Nvidia Quadro CX grsphics accellerator card for CS4.  The card utilizes DDR3 high speed graphics memory, a CUDA parallel computing processor, and dual display port/DVI/and analog DAC outputs.  The graphics processor has hardware optimized shader capabilities as well as H.264 rendering technology.  The card is compatible with Win XP, Vista, Linux, Solaris and utilizes a PCI express interface.

Although the CS3 and CS4 packages run on standard (non-optimzed) hardware, the trend is to special multi-media editing and post production machines with high performance features.  These features are designed to handle the large data sizes and high thoughput required to process HD video at full 24 FPS or higher frame rates.

Diane Chatterjee for Pallab Chatterjee