Pallab’s Place

Mentor kicked off their 2008 User Group event in Santa Clara this week, with a very good morning attendance for the day after the election and a huge traffic accident messing up traffic for miles in most directions headed towards the event.

The morning had two keynote speakers, Design-to-Silicon VP Joe Sawicki from Mentor and Chad Hawkinson VP of Vertical Market Strategy from PTC discussing a joint program and direction with Mentor. Joe’s Design-to-Silicon group covers the new combo of Olympic SOC, the Calibre franchise and the Test Kompress products. As a different spin on the technology pitch, the discussion was nicely high level and was an overview of some of the design/build information from the SOC implementation perspective and how tools address the whole life cycle of the product creation through production release.

The presentation was thankfully short on the standard DFM SEM photos, the obligatory random defect? photo that has been shown since the late 70′s and the Litho related contour? plots. The presentation, however, did show a strength for Mentor of understanding the IT impact of the current process technology and their approach to tackling the issues. As the process technologies scale down, the amount of content in the designs (geometries, firmware, gates, layers of interconnect, manufacturing/lithography steps involved) does not scale linearly. As a result, the new designs require several orders of magnitude more data to be processed in an ever shortening product development cycle. Mentor has addressed this with aggressive adoption of multi-core, multi-thread and distributed processing for their tools. The methodology includes true scaling from single CPU (multi-core) environments to full cloud computing environments to best optimize through put for design at the IP to SOC level.

The new optimization message for the 45nm and below era is now targeted at workflow optimization as is seen in data reduction, Multi-Corner Multi-Mode (MCMM) analysis, Multi-core Multi-threaded computer environments and the understanding of both technical drivers and business context as parts of the current design flow. The new workflow includes the Olympus SOC product as the central evaluation engine for the variability and power design / analysis issues, the incorporation of CAA (Critical Area Analysis), LFD (Litho Friendly Design) and CMP (Planarity modeling) into the DFM tools and the addition of Yield learning to t the Test Kompress production test environment. This keynote acted as a lead-in to the Calibre DFM roadmap held later that same day.

The second keynote addressed the larger system aspect of the Mentor product offerings. It was presented by PTC and discussed the combined workflow of the PTC MCAD (Mechanical CAD) & PLM products and the Mentor ECAD (Electrical CAD) tools for PCB and system firmware. The new system environment includes interaction in component & board design, revision control, user software/firmware and industrial design aspects of a product development program. The keynote represents one of several partnerships in development at Mentor on the path of component, software, RCS and PLM space. One of the keys in he integration is verification and validation of the design

Mentor also presented thier Calibre DFM roadmap that afternoon. The discussion focused on the new members of the Calbre family – Calibre YA (Yield Analyzer), Calibre LFD (Litho Friendly Design), Calibre YE (Yield Enhancer with Smart Fill Technology) and Calibre CMPA (CMP Planarization Analyzer).

The YA product is an integration of the prior Mentor CAA product with the tools that were brought in from the Ponte acquistion. The product is incorporated into the RVE debug environment and has support for both library characterization level and the full chip level.

The LFD product incorporates variability analysis and identifies design robustness that helps minimize litho related fallout. One of the major enhancements is the ability to perform this analysis in a time scale that is applicable to use in a normal design cycle. Prior generations of tools from vendors in the EDA space, were not capable of producing this level of quality of results in a cycle time that could actually be used as part of a design flow. These enhancements are partially responsible, in addition ot partnering arrangments, to the approval of the tool in the new TSMC Version 9 reference flow.

The CMPA and YE tools are related to both density and litho aspects of the interconnect fill. The YE product uses a new algorithm for planarization fill called SmartFill. This not only operates in 40-50% of the runtime of prior traditional dummy fill techniques but is 3D aware and supports non-rectangular fill so that performance of the fill is optimized. The CMPA tool incorporates features of the new eqDRC capability to allow for equation based descriptions of the design rules. As these features are depth of field sensitive, the tool targets and minimizes overfilling with dummy metal?.

Future directions include Reduced Design Rules (RDR) Physical Verification (PV) that is grid oriented and context awareness for rules.

As a change from the traditional PV direction at the User Group Meetings, the Calbre and Design to Silicon platform were finally messaging the whole flow of the tools from design entry, physical design, verification and test rather than a series of point tools that the customer has to integrate themselves. The support and service model as well as design interoperability that hte customers have been asking about and that they have been presenting results on for years. It is good to see the direction acknowledged and finally moving Mentor from a point to provider to being a solution provider.

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