Archive for October, 2008

Oct 16 2008

Pilotless Cadence and the wayward direction of EDA

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The latest changes at Cadence (Fister’s departure along with his gang of VPs) seems to have surprised many, but to most of the people in the design community it was no big shock.  It is just the current state of volatility in a correcting industry that may not survive the correction.  Unlike the stock market and the big investment firms, the government is not planning to use tax dollars to shore up a small boutique industry.

The sector has been self-victimized by the same sort “creative” accounting practices that plagued the dot.bomb craze and the current energy/real estate debacles along with an overall lack of cohesion for a common purpose.  This has resulted in the EDA sector having difficulty justifying making growth, realistic booking goals, a consistent definition of what industries make up the segment and the admission that the cost of development of electronic products (the end customer marketplace) has resulted in a dwindling number of customers that can afford their products.  Cadence being one of the bigger players in the field and promoting the house of cards, is just having an implosion at the leading edge.

What is interesting about the industry and the current situation at Cadence, Synopsys, Mentor and Magma is that the technology they have is actually quite sound and innovative.  To make a very gross high level generalization – Cadence and Magma are having problems with the financial community due to validation and forecast of booking and long term revenue based on not showing the global reduction in design starts, Synopsys and Mentor are getting beat up in the market because they are projecting conservative verifiable estimates which shows slow/no growth in a declining economy.  Translation – if you push the numbers, they street dumps you, if you play the numbers close, the street crucifies you – either way EDA as a sector has a problem.

The recent management at Cadence seemed to be operating under the assumption that their products were simply shrink-wrappable components that could be sold to anyone with the money to buy them.  They also followed the standard product/stocking distributor/retailer premise that new products are at a premium and you heavily discount to clear old products from inventory.  Unfortunately, EDA is a long life cycle business where the maintenance and service revenue from these older products (i.e. simulation tools, custom design, pcb) account for significant portions of the base revenue stream.  These sort of decisions are being made by multiple companies who still believe that EDA is a valid standalone sector.  The reality is that the EDA biz unit came from the electronics supply chain for a full system product life cycle program, and that breakout of “component design creation” as a parallel sector is reaching maturity and the interaction/integration of the tools, planning and manufacturing has to be re-integrated into the product cycle.

So where are we – you have a couple of big boats in the water, without a destination for where they are headed, one does not even have anyone steering the ship.  You have a couple of big boats staying in the middle of the river, heading slowiy upstream and betting that things are better there, but being careful to not crash the boat.  The rest of the private guys are just blinding following in the wakes of these boats, hoping to be acquired and brought on board, even getting on board with the directionless boats.  It would seem, the best bet is it to stop the drifting, nuke the directionaless boats and send the people out on life rafts to new industries, and redirect the two good boats to the semiconductor component and equipment channels where there is at least a positive TAM still available.

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Oct 16 2008

Cadence SMO: more folks on the light-source bandwagon

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Following the recent announcement from Mentor/IBM Cadence’s Design-to-Manufacturing (D2M) solution now includes Source Mask Optimization.  This computational technology was developed jointly with Tessera Technologies.  Tessera is best known in the high density packaging field, however they had a prior acquisition of Digital Optics a leader in illumination sources for industrial applications.

The technology is targeted as allowing for the identification, selection and modeling of both standard illumination patterns (quad, dipole, etc) as well as custom patterns available with off-axis illumination.  The result should be design optimized illumination that is hierarchically constructed to support a single optimized illumination pattern for the whole reticle area.  Similarly to the Mentor/IBM announcement, there are no production lithography tools currently using programable illuminations sources that can use this technology.  Where the Mentor solution is targeting masking and fabrication partners for the development of the technology, Cadence is moving one step earlier in the life cycle by partnering with a component supplier who may be selected as part of the stepper manufacturer’s equipment.

The technique is not targeted at just 22nm, rather it is a generalized approach that can address all sub-wavelength technologies.  The advancement of the technology should result in a more usable set of “working design rules’ rather than the complex group-by-group decisions on required rules, optional rules and suggested rules currently presented by the wafer fabs.

The solution is part of the Cadence Process and Proximity Compensation (PPC) technolgy offering.  It supports bith single and double patterning solutions, is targeted at high throughput and features enhanced rapid design convergence (single digit iterations).  Cadence/Tessera’s simulation have shown that the use of these techniques results in an improvement in process window yield.

As in the other releases in the SMO arena, it is a watch and see technology to determine if (A) the equipment manufacturers can support/adopt such a technology without impacting throughput and reliability, (B) if the fabs and processes can provide support for this additional level of variability to the deign community and most importantly ( C) if the cost of implementing the technology and its associated simulation/IT infrastructure requirements can justify the return on yield for end semiconductor products.

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Oct 14 2008

Mentor Olympus-SOC: Adding parallelism to Design Closure

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Mentor just introduced their next module to support parallel processing in the Olympus SOC product line. The newest piece is the timing and design optimization portion. These continue the simultaneous Multi-Corner Multi-Mode (MCMM) processing in the physical design arena. The product enhancement is being presented as a paradigm shift for sub-wavelength SOC design.

The premise is that the serial timing closure (timing analysis, goal identification, design re-optimization and then multiple iterations) gets excessively long in 65nm and below processes due to the large variety of corners, modes and design optimization techniques available. The Olympus engine inherently addresses the problem of the MCMM space by creating solution scenarios for the engine to solve. These are a space consisting of simulation states like Power1-Corner1-Control_state1, Power1-Corner2-Control_state1, Power2-Corner1-Control_state2, etc. The new enhancement is for making the timing closeure portion a SMP (Single Memory Parallelization) application for multi-core, multi-thread processors. This allows these multiple simulation states to be solved simultaneously with adjacent cores. As there is already a set-up engine for these tasks in Olympus-SOC, the resulting overhead is just on job launch and results gathering. This allows the performance to be at 7X for an 8 core (dual quad-core processors) machine.

Mentor has taken this a bit further than just timing closure, to includes design closure. The optimization loop includes validation and auto-selection of options such as gate sizing, buffer insertion, path duplication, and logic re-synthesis in order to achieve the timing specification required. As the environment is a physically aware system, SI, EM, IR Drop, and OPC/RET issues are also part of the constraint space for design closure. They use these optimization techniques in addition to the MCMM environment, to identify a solution that meets the timing requirement or indicates that constraints cannot be met.

The automated selection of solutions for the traditional timing closure, including SI, EM, etc, has a known history of acceptance within the design community. The extension to the MCMM decision space may also be accepted in the design community, provided there is traceability to the decision path that was used to find the solution. In these two cases, the decision on meets the criteria or not is a fairly binary yes/no decision.

The paradigm shift that is being presented is not really the adoption of parallel processing to the timing closure task, nor is it the further applicability of the physical awareness to parallel processing. It is primarily the automated selection of design closure alternatives in context of the physical views. As these design optimization solutions have both structural and functional characteristics, the selection of the solution method has traditionally been steered by the designer based on the review of available solutions that are presented. For a large number of the cases, the involvement of the designer to select the tradeoffs in the structural design is not required, as there are usually one leading solution to the design space. The main question as a result of the product release, is if the design community will embrace the automated selection of solutions for the entire design space, and how much manual intervention is supported and easily allowed. If the product is architected correctly, as Mentor is claiming and is being proclaimed in the customer testimonials, then the market will see a big winner and a paradigm shift, otherwise, it is just another one.

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