Archive for September, 2008

Sep 25 2008

Litho progress for 22nm – IBM / Mentor / et al

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Progress on the realization of 22nm wafer fabrication has moved a step closer with the new joint development program between IBM, Mentor Graphics and Toppan Photomask. Coordinated out of the IBM East Fishkill facility (Hudson Valley area of NY) advanced development of a new approach for optical resolution of the critical masking operations for the 22nm node is progressing. The direction be targeted is bringing advanced computing skills to the semiconductor manufacturing ecosystem, not just the design phase utilizing DFM and traditional mask preparation tools.

The IBM facility is a current 140,000 sq. ft, approx 4000 wafer/week 300mm facility with an in progress of being configured 72,000 sq. ft annex. The main fab floor is for 130nm, 90nm, and 65nm production at this time. The annex is in phase 1 at this time and is supporting a mix of 65nm/45nm production and 45nm/32nm process development in approx 40,000 sq. ft. Phase 2 will be the balance of 32,000 sq ft and be targeted for 32nm manufacturing and 22nm development. Process and lithography development down to the 15nm node is being done at their partner facility the College of Nanoscale Science and Engineering at the University of Albany.

The new method is based on expanding some technical and business concepts: (1) computational lithography (CL) which incorporating a manufacturing tool control called Source Mask Optimization (SMO) with Mentor Graphics and Toppan Photomask; (2) exploring development options and strategies through a TCAD based virtual fab in conjunction with Rensselaer Polytechnic Institute (RPI) and (3) design technology co-optimization that is identifying directly measurable manufacturing rules and techniques as a joint effort between Mentor and IBM.

The CL portion is an extension of the existing DFM flow which has focused on just physical design database adjustments using OPC and other traditional MDP products. Mentor has already demonstrated the expansion of their Calibre products to support distributed. multi-threaded, multi-core and other high capacity compute environments. The advanced development work with IBM will include fundamental research on applications with GPUs, the IBM Cell BE processor, and other engines that may be used in a cloud computing or supercomputer environment. The need for this is to provide rapid turnaround on the complex problem solving for the new imaging simulations. The main ideal of the new CL was to develop a method of providing lithographic solutions for specific areas of the chip being processed fast enough to be usable on the factory floor.

This manufacturing floor solution would be coupled with in development, but yet to be available 22nm masking equipment, that can use a programmable or variable light source. Current masking equipment uses fixed illumination sources for an entire reticle area. The added flexibility of SMO would allow for function specific and portions of the reticle (e.g. memory cores, control logic, high speed paths) to not only be optimized with traditional DFM tools, but also add the new dimension of source style (single point, dipole, quad, etc) in order to allow for imaging the 22nm process. This SMO will reduce the high amount of complexity of the data on the mask, and shift some of the complexity to the masking equipment and the light source. The impact will now be both mask and source simulation data processing. Toppan Photomask is participating in this portion of the program to help incorporate constraints on the reticle preparation, use and defect inspection & repair.

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Sep 24 2008

Jabil Circuit – Localized Supply Chain Model

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Jabil Circuit has been in the electronics manufacturing and supply chain business since 1966. Historically, they were best known for their subcontract manufacturing of PC Boards and enclosures. In the late 90′s – early 2000′s they added in the full supply chain support for the electronic product development market.

In recent discussions with Jabil, they have refined their model and are expanding in two areas – localized supply chain implementation and semiconductor supply chain. The driving forces for this refinement is minimizing the cost and time associated with the logistics of material movement from component production to test to system assembly. In the medial and instrumentation space, the localized supply chain has focused on supporting and supplying ROHS compliant services and facilities as a migration path for their customers. This approach is being targeted at a global expansion model after strong success in North America, solid migration into the European community and early phase in Asia and the Pacific Rim.

The need for this model is to support the increasing diversity of low & mid volume high product mix applications. These applications need a supply chain that not only includes standard subcontract manufacturing of the boards, component assembly and insertion into enclosure but also includes incomming component screening, in-production test, post-programing test, final test and packaging insertion. At this time they are operating/supporting 14 factories worldwide. On the medical side products include: digital imaging, patient monitoring, record keeping and patient bedside PCs and connected display environments, and in-hospital flatscreen/portable products.

The transition to the semiconductor supply chain was actually a customer driven direction due to the progression of System On a Chip (SOC) design. This shift resulted in a reducction of the manufacturing supply chain for a lot of systems to just a component level product, enclosures, memory and displays. In the semiconductor supply chain, they are providing customized build solutions for equipment manufacturers to be able to replica manufacture their equipment, as designed in R&D, near the point of sale, application and support of the semiconductor wafer fab. The supply chain includes both the wafer fab portion of the process as well as the electrical test, packaging and final test portions. The emergence of the semiconductor target model has given rise it a market split of 50% in North America and 50% in Asia primarily in Penang and Shanghi.

This supply chain model, that has been implemented by Jabil, for expansion of the subcontract manufacturing community is the new model that companies are shifting to in order to address the reduced component count of mobile electronic systems and offset the high cost of transportation for people and materials.

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Sep 10 2008

CDNLive Panel on Green Power and IT

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At the Cadence CDNLive press room there was a press targeted panel titled “Green Power, Smart Power, and the Next Generation of IT�.  The panel was moderated by John Blyler EIC of Chip Design Magazine, and the panelists were: Ted Vucurevich of Cadence, Nikhil Jayaram of Cisco, Dr. J. Antonio Carballo of IBM Venture Capital Group, Dr. Jan Rabaey of UC Berkeley, and Carl Guardino of the Silicon Valley Leadership Group (SVLG).

John introduced the subject of the panel by defining the scope of green power as it pertained to this panel.  The understanding was low power and power use efficiency has always been a criteria of design, just not one of top constraints.  Now, the shift has been made to address eco-friendly design which is a multi-domain, multi-sector, full design chain for both the component creation (IC) and the electronic system that uses the component.

The panelists discussed the background on the importance of “greening� the designs and the energy analysis focus on the IT portion.  Cadence indicated that it is a supply chain issue and the key was the identification and optimization of “energy productivity� which is a measure of useful power.

Cisco focused the discussions on the datacenter portion of the IT infrastructure as the energy target.  Nikhil identified that highest concentration of power use in the IT environment was the datacenters, and that most large installation now have an OPEX that exceed the CAPEX for these datacenters.  This places power as a high priority for a number of system applications.

IBM Venture Capital has been doing a lot of work in China and North America for the IT space.  The China market has 100% of it new design wins having a full identified energy efficiency target and power utilization form factor.  From an energy management perspective, the mobile marketplace is a “standby energy� market rather than an “active energy� market, and thus does not really enter into the full environment impact discussions as do the datacenters.  At this time, they are seeing over $1BUSD being spent for “green computing�, and growing.

Dr Rabaey made the connection that the base issues have been around for a long time and significant progress has been made, even with his own research, since the 1980′s.  The key to addressing and handling the energy efficiency issues is to quantify the use model through sensors to drive data collection and analysis.  This will provide the basis to develop deterministic models for energy use corrolated to activities of the equipment and then optimization techniques can be developed and applied.  This concept was referred to as a “societal information technology networkâ€?.

Carl started his discussion with the observation that when David Packard started the SVLG over 30 years ago, one of the key issues was energy use.  The eco-system for IT in both centralized and distributed implementations, is a system that is beyond on the scope of full modeling for engineering optimization at this time.  The need for this optimization and the driving factor on energy efficiencies of these datacenters is they currently consume 1.5% of the total energy used in the US and it is growing.  The solution to this problem and the reduction of energy use is going to have to be a collaborative task from members of the whole supply chain in the IT datacenter market.

The panel discussed aspects of the problem and summarized the panel with the observation that the solution was a multi-domain solution covering electrical / mechanical / thermal / and software related issues.  The consensus of the panelists was that the solution path the most immediate and supportable solutions would be a hardware based solution rather than a software solution.  This hardware would be deterministic in design and the use optimization would be provided by targeted application specific software.

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