Archive for July, 2008

Jul 09 2008

Place and Route at DAC’08

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This is a summary of the place and route tools that were shown at DAC. The report is being presented in trip report style as observed and attended by James Benouis, of Iron Gate Technology. The exhibiting vendors that were visited were Magma, Mentor, Synopsys, Atop Tech, Jspeed and Pyxis.  Also at the show, but not exhibiting was TeraRoute.


To start, I got the crazy idea to show up at DAC with a benchmark on my thumb drive. I didn’t bring just any benchmark either, but one of the gnarliest routing benchmarks I have ever come across. This congestion map from hell 250K component design, with embedded blocks, has crushed mere mortal routers and humbled some of the best. I invited all of the router companies at DAC to take a stab at it.  All companies had the option to decline participating, or give it a crack and opt out anonymously.


Magma –


I was the only demo attendee at Magma, and already somewhat familiar with Talus, so the presenter suggested that we move quickly through the slides and do an old school one-on-one demo.  The thrust of the Talus presentation focused on MCMM and CTS aspects with some talk of multi-threading capabilities and DFM. The small demo example took five minutes to run live.  It was 30K components with six scenarios (3 corners and 3 clocks).  While we were reviewing Talus CTS “robustness? output files showing the delta between delays across all scenarios, the log indicated 1.36GB memory.  This reflects that a 1M cell design would take over 30GB of memory.  Magma claimed that Talus with a 1M component design and 44 scenarios took eight hours in a 33GB memory footprint versus fifteen hours and 40GB by the competition. This is where Magma surprised me. The next few slides showed not only Magma’s progress in reducing their memory footprint by 30% over the last several releases; but it also contained an admission that Magma’s final output contains errors.  What was truly shocking was that Magma was not only admitting that they had errors, but acknowledging the fact that errors are now considered unacceptable, and addressing a path to reduce/eliminate them.


Mentor –


At the Mentor Design-to-Silicon press conference, Joe Sawicki, while anecdotally referring to the typical buyer’s remorse on a software acquisition, stated that what was particularly pleasant about the Sierra Acquisition was “what we found out we didn’t know was how good this stuff was?.   Mr. Sawicki went on to say that “rather than running into problems, what we (Mentor) have run into are more and more opportunities?.  Mentor indicated that, in first 6 months, they had completed 8 design in’s at major semiconductor companies and over had the P&R tools as part of 100 tapeouts, mostly at 65nm and below. Mentor claimed they mostly leveraged their superior MCMM (Multi Corner, Multi Mode) capability to get in the door, and from there, saw further opportunities in the area of clock tree and power.  In my opinion, at this time, Olympus is not a full chip assembler, but more of a block builder.


I also attended the floor demo for Mentor Olympus.  They boasted of a 100M gate flat design, although the demo design was 80K gates in TSMC 65LP running at 200/217Mhz. They chose a dual voltage MCMM design with gated power and clocks and multiple voltage islands to demonstrate some of the strong points of Olympus. The demo was more of a great mini-symposium on modern design challenges and lacked the rubber meeting the road of where Olympus solved those problems. The presenter had a lot of material to cover and was rushed to squeeze it all in.  On a humorous note, a slide in the CTS portion of the presentation contained the claim that Olympus “Auto-magically? balances buffer trees.


The Olympus technology, coupled with existing caliber tools, opens up some exciting possibilities for Mentor. With Olympus, it’s possible Mentor could be a top player in the P&R space. Mentors claim of 100+ Olympus tapeouts in 6moths would, at quick glance, gives the impression that they have leapfrogged Atop by a year. 


Synopsys –


I attended a live routing demo of Synopsys’ IC Compiler’s new router: Z-route.   The demo pretty much amounted to showing off and, judging by the reactions of the packed room, it worked. The demo was to live route a 10M gate design for TSMC 65nm, 8 layer metal, 2.7M components and 15 hard macros.  The route ran on a 2.6Ghz Linux box, with 8 cores and 32GB of memory, and completed in less than 30 minutes.  The Z-route product is an all-new development, with no shared lines of code from previous routers, based on a new architecture they call “realistic connectivity.? The concept of “realistic connectivity? considers all connections and subsequent interactions from timing to lithography.  Z-route runs on the Milkyway database and is MCMM and DFM aware, however, the focus of the presentation was on performance, capacity and QOR.


According to Synopsys, Z-route runs three to four times faster on a single core than their previous single-thread engine.  They claimed 2% less wire length, 10% less vias, 42% less single vias and a 92% double via coverage.  Although Zroute is so new that Synopsys did not claim any tapeouts, they did fall back on IC compiler’s claimed pedigree of previous 300+ tapeouts.


Atop Tech –


The first thing I did when I arrived at the Atop booth was to sign up for the Broadcom lunch the next day and schedule a demo for later that afternoon. When I came back for the demo, I was told that the Broadcom lunch was closed to the press and I was taken off the list. They even took my printed invitation back.  So, while I can’t tell you about Atop Tech at Broadcom, I can give you the gist of the Aprisa presentation/demo. 


Atop gave a brief company background, introducing themselves as Ex- Avanti guys, who have raised 14M in capital, and claim over 20 tapeouts at Broadcom and Raza Micro. They segued into the technical portion of the presentation by asking the audience if they had read the anonymous posting at ESNUG reviewing recent Atop success.  In the presentation, performance numbers on Aprisa were included in the slides, though too quickly to copy, and the numbers were not made available afterward.


The technical focus of the demo was on the clock tree.  I asked if they provided hierarchical netlist insertion, a feature that the more mature competition added in later versions. Their answer was ,?yah,yah,yah? and, after a couple “yah,yah,yah’s,?  I stopped asking questions. It was clear, technical questions about the tool were interrupting a highly polished marketing presentation.  The overall AtopTech pitch was “we do everything the other guys do, just 10-15% better?.  And, if you need more proof, unless you are press, go to the Broadcom lunch, in which no printed copy of the presentation are available except for the anonymous posting on Deep Chip.


With respect to the matter of errors as discussed with Magma, if you read to the bottom of the Atop ESNUG post, you will see that one of the cons listed by anonymous users is that Aprisa also has errors in the final GDSII.


On the business side, AtopTech appears to be focusing more on an acquisition play than trying to steal business from their rivals like Magma. Even if the Aprisa product is 10-15% better in all areas as claimed by Atop, it lacks synthesis and is only as a block builder.  If you are looking to replace a full flow like Talus, it probably won’t be with an unproven tool that also makes errors.  For Atop to weigh in as a solid competitor at DAC46 in San Francisco, they need to show up with revenue and not just another anonymous endorsement. 


Jspeed –


Making its DAC debut in Anaheim was the Jaguar Router by Jspeed. Jaguar is the sole creation of Dr. James Ho, University Professor and former Cadence IC-Craftsman developer.  Founded in 2006 and Based out of San Jose, Jspeed can best be described as an early stage technology.  Although Jspeed claims some promising early results with Jaguar, the router is clearly in alpha. Ulike most commercial routers, JRoute does global routing on-the-fly.  With two employees at DAC, Dr. Ho and his wife, Jspeed’s main goal seemed to be drumming up interest in yet another router and finding potential beta customers.  Jspeed uses a hybrid gridded and shape based approach and claims to address DFM issues. Jaguar is designed to exceed the competition in speed and capacity.  In my demo of Jaguar, Jspeed did not show a viewer to observe or check its output. therefore, without being able to view any output, it was hard to validate the features. 


Pyxis –


Of the returning high performance routers officially at DAC, the Nexus router from Pyxis is becoming mature.  Pyxis claims that Nexus provides improvements in timing, power, and yield all within runtimes comparable to the rest of the industry.  The Nexus router has been developed in Austin by a team of industry veterans and patent holders in the areas of global routing and timing.  An exceptional member of the Pyxis team is Joe Rameh, he has a PHD, over 15 years of EDA experience and is an ace at Guitar Hero.  Pyxis claims Microsoft Xbox as a customer for their router and this relationship is probably the basis of Joe’s GH skills.


Pyxis was the only company that participated in my “live benchmark? challenge. Since they were the only participant, there are no comparative results. Pyxis does deserve credit, not only for participating, which showed confidence, but also for the result they produced.  They did complete the benchmark design, which was no trivial task. This design was truly from hell and Pyxis was able to handle it soundly.


TeraRoute –


The TeraRoute guys showed up at DAC with no booth, but with an interesting story.  TeraRoute was founded in 2004 by John Cooper of Cooper & Chyan fame. TeraRoute had booths at DAC in ‘05 and ‘06, but after licensing their source code to a major EDA vendor for an undisclosed amout, they shifted their focus towards technology licensing rather than end-user/individual license sales.  TeraRoute also has no global router.   Instead, T-route, a Macroshape based router, utilizes a route strategy scheduler and on the fly contextual decisions to handle route planning. T-route also claims to be SI and DFM aware.  From the laptop demo they gave me at the Hilton, I can definitely say this is one fast shape based router.


Other P&R tools –


This was a summary of observations and attendance of the P&R tools that were present at the DAC ’08 show.  There are other routers on the market, including those from Cadence which were not at the show and, as such, not part of this summary.


James Benouis, Iron Gate Technologies

Edited by Pallab Chatterjee, SiliconMap/Extension Media


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