Jun 20 2008
Analog Designer Perspective on Analog at DAC 2008
This year DAC is being touted as the “Year of Analog�. Yet again, another under-developed sector, that has customers without a budget, and that require a very large diversity of solutions around very few core engines is supposed to be EDA’s salvation.
I agree on many aspects that the Analog and Mixed Signal markets have been under-served by EDA, and as a result there are now many tool vendors suppling products into the space, however the real solution providers in this space took a long time to get to the market, stabilize their products and work with the customers to develop usable solutions. This is not the quick entry marketplace due to the voluminous legacy data (over 30 years worth) that exists and needs to “participate� in the new tool environment.
The better title would be “Year of Device Level Design�. Then all the digital IP libraries being rightfully redesigned and ported to new sub-wavelength processes using re-architectured and re-engineered device level tools would be the market. This market has budgets, customers and is more systematic from a tool requirement and use model perspective.
In any event, it is “analog� so the belief is that the real designers working at any level below verilog will now have new tools. In my short review of products appearing at DAC, I have based by comments either on (A) prior design knowledge of either directly working with the products, or working with customers working directly with the products, or (B) new assessment of the product based on the capabilities of the DAC demo and the ability for the floor staff to intelligently answer simple questions about their company and products.
[NOTE: Due to an abreviated DAC Schedule, I did not get a chance to visit AWR or Magma, their product reviews will appear next week as another editor James Benouis covered their products]
Vendors who knew what Polygon Layout, Schematic Capture, Netlist, and Device Simulators were used for, had customers, and had product demo that indicated such:
Simucad, Berkeley Design Automation, Solido, Pulsic, SpringSoft, Mentor, Synopsys (simulator products only)
On the right track, but still early stage :
SynCira, Ciranova (PhyCell Studio only), Nassentric, Synopsys (custom layout)
Without a clue :
The REST of the DAC exhibitor with layout editors and new simulators and most of the new and old products from these suppliers.
This assessment was based on their global inability to answer the following questions for the product or have a demo that any remotely related to useful steps of the analog design process.
Q1Â Â Â What database format can your read in and out for going to mask or legacy design capture?
Q2Â Â Â What simulation / verification / DFM tool do you interface with and with what data format?
Q3Â Â Â Can you hardcopy (make a printout) of any of the stuff on the screen?
Q4Â Â Â Do you have any fab or EDA relationships to get the tech file info?
Q5Â Â Â Has anyone at your company actually designed an analog block and released it to a fab for manufacture and test – and been responsible for those stages – at your company?
Sadly, the majority of “new Analog companiesâ€? to save EDA were averaging having an answer for only 1 out of 5 and that was Q3 – with a general answer of NO.
Not a happy day in EDA and Analog town – just another one, with the Cadence Analog tools still holding the majority of the new license and maintenance market.
PC
Hi Pallab,
I especially like your Q5: “Has anyone at your company actually designed an analog block and released it to a fab for manufacture and test – and been responsible for those stages – at your company?”. This is the plague of the “non-cognoscenti” that I have been writing about in my blog. I invite you to check out http://synopsysoc.org/analoginsights/?p=18 and http://synopsysoc.org/analoginsights/?p=19
Regards,
Mike Demler
Without a clue???
Without a clue :
The REST of the DAC exhibitor with layout editors and new simulators and most of the new and old products from these suppliers.
This assessment was based on their global inability to answer the following questions for the product or have a demo that any remotely related to useful steps of the analog design process.
Q1 What database format can your read in and out for going to mask or legacy design capture?
A: Openaccess
—
Q2 What simulation / verification / DFM tool do you interface with and with what data format?
A:
Simulation: Spectre, Hspice, Gnucap, Verilogams Netlisters (built in and customizable.
Verification: We save to Openaccess
—
Q3 Can you hardcopy (make a printout) of any of the stuff on the screen?
A: Everyone can. What am I missing?
—
Q4 Do you have any fab or EDA relationships to get the tech file info?
A: Do you really think that any CAD company can create tools without proving them out on the technology? This is where the rubber hits the road. We prove out our tools on 130, 90, 65, and 45. I am sure our competitors do as well.
—
Q5 Has anyone at your company actually designed an analog block and released it to a fab for manufacture and test – and been responsible for those stages – at your company?
A: Me. A/D converters, PLL’s, PWM’s, References, etc.
—
Question for you:
I don’t remember you coming to our booth. Why didn’t you? Even John Cooley came by for a demo, and he represents digital.
Clif:
First off I did visit your booth, I attended a demo from 100pm-130pm on Monday afternoon 6/9, there were several other companies also attending the demo. At the conclusion, since you were answering questions with the potential customers, you asked me if it was OK to finish questions with your marketing person and we continued to discuss things for about 20minutes.
As the discussion could not identify any foundry or IP partners who could be disclosed, specific process technologies that had been used (i.e. TSMC 90G, etc) or reference customers, I put you in the bin of “unverified”.
As far as verification, you indicated in the demo, that you had your own verification tool for “correct by construction” and you could implement any of the functions from Hercules, Calibre or Assura in your tool OR the customer could output to those tools. The marketing person did not which formats were supported for the export to MDP, DRC, LVS, or DFM tools. He also indicated that your company has never verified the compatiblity of the database with current masking technologies and that you did not have any mask making/litho relationships in place or planned.
The question about hardcopy related to the difference from low resolution screen capture mode through large format plotter and multi-sheet printing (critical for analog designers) with fill patterns, and if the screen fills and colors were the same as hardcopy or mapped. You mentioned in the demo, that “of course it can hardcopy” which is not an answer to the question as posed.
Clif, as the show was busy, and your booth was crowded, I was specifically not “picking out” your company as one that could not answer these questions with any consistancy or verification. I binned you with the others that were not able to provide complete answers to these questions.
Finally, Congratulations on the show! I guess your booth was well received and busy if you did not remember a rather “contentious” 1 hour discussion with the press the first day of the show.
Pallab Chatterjee – Reginal Managing Editor
Pallab
It makes no sense for me to push anyone to a marketing guy, and I don’t know why you would seek out anybody else but me on a technical question. That is my job function.
Our export strategy is to use OA as our database so that anyone can launch 3rd party tools from there. That is the purpose of OA. We netlist all formats for simulators, since we don’t have our own simulator.
Hit the Print/Plot icon. We are QT based, so we can handle all platforms. Linux can handle plotting through cups. I think all the vendors can do this, and I don’t think this is a major feature.
As far as foundry support, I need to challenge your statement. Our demo was in 65nm. That isn’t a current masking technology? We (including me) have read manuals from cover to cover (including the LOD, WPE, and other DFM and analog recommended rules), and I cannot imagine any one of our competitors (including ourselves) not testing the tools on foundries processes. The statement that this has not been verified is false. Do you really think a company doing layout wouldn’t verify design rules.
I already know what your next question is going to be, and I won’t answer it.
Cliff