Archive for June, 2008

Jun 20 2008

Designers Perspective on IP at DAC 08

Published by under Uncategorized

The data collection that was performed and the comments were provided by James Benouis of IronGate Technologies. I performed the editing function on these opinions.

I started on the show floor with a blank notebook , a list of companies to talk to and a few questions. The actual survey data came out pretty tabular, I included the Soft IP companies even though we probably won’t use them just to be thorough. It was interesting to smell test the soft IP guys since it’s so easy to say you have silicon back when it’s not yours and hide behind that you can’t reveal your customers (or more like customer) . I think the Tensilica guys were extra fishy. Novelics didn’t convince me either.

As for the Hard IP guys, the real men with actual validated wafers, it was pretty much what we thought. I would say that best case the industry is on the cusp of broad 65nm roll-out and anticipating first 45nm silicon by the end of the year. Many of the companies that couldn’t legitimately claim 65nm validated silicon have taped out but don’t’ have silicon back or so they claim. John Perry at Silicon Image claims they have taped our 65nm and 45nm for Silicon Image internally but that they don’t have any IP publicly available. Kilo Pass claims to have memory IP back in TSMC 65nm LP. However TSMC requires 1000hr qualification which they are only 500 hrs through. This is typical of most IP companies at DAC. If you leave out pure Asian market guys at 180nm and 130nm, these are companies that have no plans at 65 and below and only one said they were looking at 90nm. Looking at it huh? I’m sure looking is all they will be doing unless it’s a high volume low-tech part. The only 65nm product that we might see out of Asia consumer market in the next 18 months will be in a talking greeting card or gaming systems right?

I will now give you my take on the most interesting angle on IP vending at an EDA trade show. When Mentor first got into the IP market we all questioned the fairness of a tool provider becoming an IP provider. Mentor began the trend of making EDA companies both simultaneously vendors and competitors. It took the market place a few years to adjust but we came to accept these conflicts of interest as part of the new terrain.

What a company needs to offer leading edge IP at 65nm and below is the Software, the foundry relationships, and the IP developers – although some would argue that the later is optional. Synopsys claims to have all three sides of the triangle. Synopsys is also the market leader in Software sales and with Cadence’s tarnished relationship it’s fair to say Synopsys has the best relationships with the foundries. How did third position Mentor go from a pioneer IP provider to completely out of the IP game? They didn’t have all three sides. Ok they didn’t really have one good side. If you aren’t a player in the IP game you have little or no chance of maintaining a dominant market position in EDA. This might explain Cadences’ acquisition of ChipEstitmate. The ChipEstimate deal came right on the heels of the Cadence fall from grace. Good time to shore up your weakness against the new market leader. When you are software leader or perceived to be you could maybe afford to have a weak IP story. But as a tarnished silver medalist Cadence had to shore up their soft spot in a dual with Synopsys – IP baby!

People were also talking a lot about skipping technology nodes. With the tooling cycle so long and with high cost of getting tools and process on-line at lower geometries contrast against shorter product life and market window, skipping technology nodes is will continue to be a necessary strategy at least for the small guys.

I did not get a chance to talk to the IP guys about their 180nm and 130nm offerings as those were supposed to be old products. These are just some of the thoughts and words floating around the DAC floor with the IP guys.

Report by James Benouis

Edited by Pallab Chatterjee

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Jun 20 2008

Analog Designer Perspective on Analog at DAC 2008

Published by under General

This year DAC is being touted as the “Year of Analog?.  Yet again, another under-developed sector, that has customers without a budget, and that require a very large diversity of solutions around very few core engines is supposed to be EDA’s salvation.

I agree on many aspects that the Analog and Mixed Signal markets have been under-served by EDA, and as a result there are now many tool vendors suppling products into the space, however the real solution providers in this space took a long time to get to the market, stabilize their products and work with the customers to develop usable solutions.  This is not the quick entry marketplace due to the voluminous legacy data (over 30 years worth) that exists and needs to “participate? in the new tool environment.

The better title would be “Year of Device Level Design?.  Then all the digital IP libraries being rightfully redesigned and ported to new sub-wavelength processes using re-architectured and re-engineered device level tools would be the market.  This market has budgets, customers and is more systematic from a tool requirement and use model perspective.

In any event, it is “analog? so the belief is that the real designers working at any level below verilog will now have new tools.  In my short review of products appearing at DAC, I have based by comments either on (A) prior design knowledge of either directly working with the products, or working with customers working directly with the products, or (B) new assessment of the product based on the capabilities of the DAC demo and the ability for the floor staff to intelligently answer simple questions about their company and products.

[NOTE: Due to an abreviated DAC Schedule, I did not get a chance to visit AWR or Magma, their product reviews will appear next week as another editor James Benouis covered their products]

Vendors who knew what Polygon Layout, Schematic Capture, Netlist, and Device Simulators were used for, had customers, and had product demo that indicated such:
Simucad, Berkeley Design Automation, Solido, Pulsic, SpringSoft, Mentor, Synopsys (simulator products only)

On the right track, but still early stage :
SynCira, Ciranova (PhyCell Studio only), Nassentric, Synopsys (custom layout)

Without a clue :
The REST of the DAC exhibitor with layout editors and new simulators and most of the new and old products from these suppliers.

This assessment was based on their global inability to answer the following questions for the product or have a demo that any remotely related to useful steps of the analog design process.
Q1    What database format can your read in and out for going to mask or legacy design capture?
Q2    What simulation / verification / DFM tool do you interface with and with what data format?
Q3    Can you hardcopy (make a printout) of any of the stuff on the screen?
Q4    Do you have any fab or EDA relationships to get the tech file info?
Q5    Has anyone at your company actually designed an analog block and released it to a fab for manufacture and test – and been responsible for those stages – at your company?
Sadly, the majority of “new Analog companies? to save EDA were averaging having an answer for only 1 out of 5 and that was Q3 – with a general answer of NO.

Not a happy day in EDA and Analog town – just another one, with the Cadence Analog tools still holding the majority of the new license and maintenance market.

PC

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