Archive for May, 2008

May 30 2008

ChipEstimate.com / Cadence – update since acquisition

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I had an opportunity to meet with Adam Traidman of ChipEstimate.com, which is now part of Cadence. The discussion centered around some of the issues and trends in sub-wavelength (130nm and below) process node IP and included an update on the status of ChipEstimate.com.

Current status of the product since the acquisition: the former Chip Estimate InCyte product is now available for sale from Cadence as the Cadence InCyte Chip Estimator and Cadence Chip Planning System. It is available in two flavors, one for mainstream fabless companies and the other for IDM’s and IFM’s (Integrated Fabless Manufacturers). The portal still has a free version (InCyte Lite) with some reduced features available for design service, startups and budgetary planning applications.

Current status of the portal since the acquisition: the ChipEstimate.com Portal is being maintained as an independent offsite portal for IP providers and information for SOC estimation/power planning and there is no anticipated change to that status. Even though Cadence will not be at DAC this year, the portal will be exhibiting and offering a series of talks from foundries and hard & soft IP providers dealing with SOC integration and IP use issues. The presentations will be provided by over 20 of the 175+ IP suppliers who have offerings detailed on the ChipEstimate.com portal.

On the topic of sub-wavelength SOC build and IP Selection, we identified 6 gating common problem areas with respect to the standardized use of IP from multiple suppliers. These issues are:

(1) The business viability, licensing model, rights of ownership and foundry relationship of the IP provider.

(2) Design data grid and its applicability to the tool flow used. As most SOCs have multiple tool flows (custom IP level, Megacell level and chip assembly level), commonality of the design grid is required for predictable performance and proper implementation of DFM / DFY correction.

(3) Abstract description, routing and blockage description. Most IP utilizes a small number of interconnect layers (2-5 metals), and the SOC’s are on processes that support up to 12 layers of metal. Application specific blockages and pre-routes must be described in order to keep the characterization of the IP from being comprimised.

(4) Multi-mode power methodology. There are a number of application based power modes (full power, standby, hibernate, display off, etc) as well as implementation strategies to achieve these modes (Switched rails, MTCMOS, etc). It is important to identify which power modes are supported by the IP providers so blocks with a common power strategy can be grouped together and avoid hundreds of thousands of gates of power control logic at the SOC level.

(5) Memories and Mixed Signal IP have parametric constraints well above and beyond traditional timing and power issues. As a result, placement of these blocks, specification of adjacencies and cross wafer variability must be addressed in addition to the nominal operational specification.

(6) I/O libraries are typically provided by both foundries and third party IP suppliers. Construction of the I/O ring with multiple power rails, ESD, simultaneous switching characteristics, ring break points and isolation regions, corner requirements, signal level shifting and logic vs memory vs analog pads is a major challenge. Currently, there is no automation or systematic meta-data methodology for transferring this information, and it relies heavily oa a service based support model and paper documentation.

As processes move to smaller geometries, these issues are getting increasingly complex, and the need to be able to compare IP offerings on a basis in addition to the base performance specification is required. At this time, ChipEstimate.com is continuing to operate as an independent portal for a large amount of this information.

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May 30 2008

Javelin Design – J360 Platform – first look

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javelin figure 1Javelin Design Automation which was formed in 2004, is releasing their first product platform the J360. The platform consists of the J360 DataWarehouse, TrueFit, TruePlan andTruePro products. The platform is targeted for use by the entire chip development chain from the business side through front end designers/chip architects and the finally to designers dealing with physical issues and chip integrators. The products available in the platform are multithreaded and support multi-core processing..

The platform has been used by several customer during its development to date, and the technology has been used for over 30 tapeouts. The J360 platform is a Specification Driven Design Feasibility environment. Other planning tools on the market focus on mapping existing IP into a design for size and power analysis, or are ESL products that are just dealing with architectural tradeoffs with no physical implementation awareness. The multi-product approach allows for a systematic automated analysis, based on the breadth of available information for a design, to be processed in any combination and have the results ‘abstracted” to relevant results through the use of targeted product modules.

The tool performs design feasability using System C, RTL, Gate Level, Hard Analog/Memory IP, clock trees, power planning, embedded controllers, standard cells, I/O, timing constraints, power constraints, and parametric goals which are maintained in the J360 DataWarehouse. The Trufit product is targeted for analysis at the program manager/business level. It deals with creating chip plans based on real design data, supports architectural design “what if” trade off analysis and create data sheets of the options. As the product is linked with actual design data, project progress can be monitored to provide the management with real time status information.

The TruePlan product is targeted at reviewing design feasability issues such as chip architecture, bus topologies, inter-block dataflow, RTL micro-architecture, modular design struction and partitioning with both “finished clean” and “in-progress dirty” RTL/netlists. This planning can be performed concurrently with the module level implementation efforts.

The TruePro product is directed towards physical chip architects, RTL designers and chip integrators who are validating that chip plans are physically realizable. Javelin uses a method called progressive prototyping which is a hierarchical chip planning methodology that is concurrent with block in context prototyping. This methodology enables teams to predict, detect, analyze and fix design problems with the chip plan prior to finalizing the netlists.

The current limitation on the system is the J360 DataWarehouse has to be populated with information about the IP being used, and thier IP partner base is still in early stages. The customers to date have been using their own custom IP developed internally, so the reduced breadth of design information from third party IP vendors has not been an issue. List price for the environment is starting at $350K.

 

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May 13 2008

NAB 2008 – Video and new hardware

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This years NAB show had a strong focus on hardware for content creation and broadcast.  Most of the custom hardware was in the form of encoders/decoders and data transport/storage.  Xilinix not only was displaying thier prototype boards and FPGA products (Virtex 4 and Virtex 5), but they were the predominant component on add-on accelerator boards available from third parties such as Thompson’s Grass Valley Group. Their prototype boards featured the Virtex 5 family of processors ans showed IP that included H.264, MPEG2 and JPEG2000 encoders & decoders and new this year,a 3GB/SDI macro.

Joining Xilinix in the Programmable device area were Mathstar, Altera, and Ambric.  Ambric showed customer applications of thier multicore DSP based architecture arrays.  These were used to make high speed encoders and decoders for both video capture and broadcast.  Thier initial product has 336 instances of a 32 bit DSP style processor.  In order to bring the product to market, they also developed a set of design and development tools that allow the user to create optimized application software.  The product currently has an H.264 and MPEG2 encoder/ decoder set on a reference board.  Thier reference customers have shown results at the level of 1 teraop/sec at 15W performance for fixed point operations.

Telarity was demoing their broadcast encoderr solutions at the event.  The high speed H.264 compliant encoder uses 7 of thier custom processors to operate the product.  The most remarkable feature was the ability for the high relability systems (dual supplies, etc) to start up in only 5 seconds to active broadcast.  Most of the systems of the market have a 30+ second startup time.
 
Sony had both a hardware and software exhibit at the show.  On the hardware side, the new products included tapeless HD cameras, OLED displays, video servers and HD projection & display products.  They were showing a full 4K projection systems with an editing station.  They also showed several large format HD displays for stadiums, houses of worship and scoreboards.  On the advanced technology side, they were showing an add-on high contrast OLED display for HD broadcast and video cameras.  Their video servers were all supporting multiple high speed (GB/s) channels and Petabyte level capacities.  Their new video cameras in the HD format are supporing 4:2:2 capture and data in MPEG2 format at 1080i resolution.  These cameras aer available in a tapeless format using high density memory cards.  Neither Sony, Panasonic or Fuji Film would comment on the soft error rate or data storage and read error rate for these cards.  At typical consumer level error rates, (typically between 1-10 part per billion), it guarantees as least 1 non-correctable error on a 16Gb card, and a high probability on the 2-8Gb products.

On the multicore front, specialty encoders and decoders have started to embrace the architecture.  However, for mainstream video processing software for Non-Linear Editing (NLE) or real time broadcast editing, the software is on its way.  At this time, the only NLE offering is Sony’s Vegas Pro package (multi-core, and 64 bit in Q3 release).  Autodesk supports multi-core processing for their Media and Entertainment modules (Smoke, Flame, Lustre, Maya, etc).  They were showing the product in thier user group event on 8 processor machines and with custom Infiniband servers.

As the format wars settled out, there were a number of companies with Blu-Ray copiers for both high and mid/low volume.  Teac was showing a new system that supported standalone copying/ duplicating of the High Def media.  Primeria also showed several duplicators, with a new sub $3000 Blu-Ray/DVD/CD printer/duplicator that utilizes a 20 disk handler.

In past NAB shows, audion was a small part of the radio broadcast sector.  Now, audio is a major portion of the video capture and playback experience.  The digital theater group, and Dolby lead the way with play back systems.  On the recording side, Holophone of Canada has a number of models of thier 5.1 surround sound microphone pod.  They also supply traditional and camera mountable mixer and multipler solutions for allowing the recording of the surround sound in a standard two channel format.  Most of the NLE tools and the pro-audio tools (from Avid, Sony, Adode) have 5.1 and 7.1 sound processing software. 

A number of new recording devices that have an increased recording quality level were introduced.  In the past, the standard was 16bits at 48KHz.  In the last few years, it has moved up to 24 bits at 96KHz.  Roland introduced two different 4 channel recorders (one hard disk, the other solid state media) that support 24 bit/192KHz data rates.  The unit supporting the SD cards were gangable to a total of 8 channels synchronized.  The hard disk unit is the “Pro? model and include time clock synchronization with a video clock.

A last section that was vistited consisted of test methods, software and hardware.  On the software testing side, eInfocchips has developed a program called Visual Quality Inspector (VQI).  The VQI product provides quantitative metrics for visual quality such as PSNR, SSIM, MSE, and MSAD.  These are normally done manually with a subjective (human) reference.  The product works with all formats of data SD, HD and Custom and has been tested up through full 444 video data. 

Tektronix also has a product for quantifing video images – the PQV500.  This product is targeted at video compression/decompression systems and format translation systems, this is a hardware product.  The balance of the products were hardware for the testing of video for the broadcast industry in SD, the transistion to HD and also to DTV.  Compression verification tools have also be created for MPEG4, MPEG3 and H.264.  Tektronix is also the founding member and coordinator of the Cerify Developer Community which is an industry consortium for video asset management providers and video service providers of all formats.

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May 13 2008

Xilinx Virtex 4QV FPGA Family

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In April Xilinx introduced a new high reliability FPGA based on the Virtex 4 family targeted for the Aerospace and Defense industry.  The Virtex 4QV product uses the same developmen software as the commercial version of the product. This gives the high reliability product access to DSP, CPU Cores, memory ineterfaces, and connectivity solutions that have known tested interfaces and functions.

The sofware development environment has special features for the Virtex 4QV family.  The TMRTool helps to auto create Triple Modular Redundant designs (best of, voting logic) for standard deciisions and logic paths.  These tools were developed with Sandia labs and include both error creation and scrubbing for particle (SEE) effects.  The design methods and the parts have been validated by the SEE consortium.  The FPGA is rated at a 300krad TID level, which after a startup space SRAM load, means minimal if any impact from in operation SEE. 

Application blocks that can be implemented and have been tested include: video compression, encoding and decoding, filtering and processing for Radar, AES, 3DEC and other encryption methods, 802.xx packet data processing, and ethernet / fiber channel bus management.  Figure 1 shows a sample functional partitioning for a design using one of the members of the product family.

The product is available in both Ceramic and Plastic packages and both are B, M and V rated for oveperation over the data of -55C to 125C.  The packages range from 640 to 960 pins.  The products are available now and have a legacy of reliability of service from being included on programs such as the Mars Lander, the Mars Rover and TACSAT.

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