Archive for April, 2008

Apr 29 2008

RSA Conference 2008

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The keynotes RSA Conference held in San Francisco followed the theme that data Security is no longer an option, it is required.  This was reiterated several times by RSA president Art Coviello who also noted the dialog box pop-up of “Are you sure?? before you submit information is the tech worlds equivalent of the old movie line “Do you feel lucky??.  A later keynote by Dept of Homeland Security Secretary Michael Chertoff identified today’s threat of cyberspace is on a par with 9/11.  Replays of the conference keynotes are available after registration at the following site:

In a move that emphasizes the direction of security, Hitachi recently purchased the long standing private company M-Tech, now called Hitachi ID.  The M-Tech acquisition fills that gap in their IT and security services offering.  Hitachi is now suited to address customers needing Identity and Asset Management solutions with full product line solution from a single provider.  This software was a needed addition to the wide variety of access control products including RFID and biometrics. The Hitachi ID software solution is currently implemented at over 200,000 users and supports single-core, multi-core and distributed processing environments.  One of the key applications is for SOX compliance reporting and access.

From a hardware perspective, there were lots of FPGA solutions for encryption/decryption of the data streams and authentication for access control.  Typical of the offering is the 10Gb AES softmacro for the Xilinix family of products that is available from Algotronix Ltd.  The IP is being offered on a 60 day/5 FPGA trial basis.  The predominant ID system for access control is still the hardware dongle with either a fixed or changing key.  Biometric ID (thumb, fingerprint, eye scan) were all still present, but were not highlighted as prominently as the software system for backing them up.  Hitachi was displaying their new finger vein scanner which is supposed to be more unique and consistently identifiable than fingerprint scanning.

One area that the software suppliers did not indicate they were addressing is the area of malware, viruses, and software intrusion in multi-core and GPU executable environments.  Shared cache systems attached to multiple core processors that also reference a single memory store have some issues with false flag generation for access control and ID confirmation applications.  At this time, none of the vendors that were asked about this problem had a definitive position on how it was addressing this problem for code installations on legacy software that was created for single core engines.

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Apr 25 2008

SNUG 2008 San Jose

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The Synopsys User Group held it San Jose event recently. The opening keynote and introduction by Aart de Geus gave the direction for products for the coming year. The talk reviewed the standard speed up of PrimeTime, VCS, ICC, verification and litho sim. These improvement were made in part to support the large shift in the semiconductor community from an IDM model to a fab lite model.

The theme of the conference was the addressing of power usage/reduction as a driving design constraint and multi-power design. A number of the power issues are being addressed by the UPF group that is part of Accellera. Accellera group is also launching a VMM consortium to promote the use and creation of open VMMmodels. The new group is called the VMM Catalyst Program and absent from its current membership are Mentor, Cadence and Magma.

With the smaller process geometries (65nm and below) requiring a reworking of device level design for library elements, Synopsys introduced some major updates of the thier custom device environment. Their device simulators (HSPICE and others) are in the process of being recoded from single processor to multi-core awareness. They also rolled out a new repackaging and reshaping of the one of the old Avanti custom design tools (Cosmos) and have updated it ti work with OA. This new tool is called Orion, and includes schematic capture and custom device generation in addition to full custom layout. They did not memtion an OA to milkiway tramsition for the tool, so the assumption is that it is an OA tool only, and hence is not addressing any historic Analog Artist Applications or designs.

The EDA community and Synopsys interestingly noted that the new processes are driving designers back to device level design. As happens every couple of years, it is “analog’s time? again. The reality is, it may very well be the time that “analog? and device level primitive design is needed, however there are no innovations in tool flows or even new points tools being made in the custom design sector. Simply improving the throughput of an existing tool without a new flow to bring data in or improve the interpretation of result, does not rr real;y fix anything. As a results, the device level simulation at Synopsis is the same but faster than last year.

Once again the PR folks showed their high levels of paranoia by restricting the press to only a few sessions rather than inviting them to the whole event, this leaves the press continuing to hear from only disgruntled users.


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Apr 07 2008

Going to NAB?

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Yes, I’m still among the living.

I’ll be attending NAB next week for Chip Design magazine. Let me know if you want to meet at the show.

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