Archive for October, 2007

Oct 16 2007

Chip Estimate New IP Services – 10/16/07

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Chip Estimate Corp provides a portal and search engine for semiconductor IP that can be used in SOCs and other custom chips.  They additionally provide yield prediction software for the overall design based on the blocks selected.  Today they announced a new free service, that will now bring their product offering to customers on the leading technology edge rather than the leading functional edge.

The semiconductor IP that is listed on their site currently includes standard product macros and IP blocks that are fully characterized and usable for designs based on the process node in questions.  Unfortunately, for companies with complex designs that require multi-year architectural and logic design schedules, the availability of IP for use 12-24 mos out or in a custom configuration, are not listed on the site.  This is due to the fact that these blocks are still in development at the IP providers and/or are not available as standard, full suite characterization due to customization requirements by the end client.

The new IP Concierge service has a simple fill in form that gets sent back to the IP providers that indicates someone is looking of these “under development cells” or a “modification” of a standard block.  The information allows the providers who are at a stage of development to work with an advance partner to “beta develop” the cells with a customer.  This will allow the end products to come out on schedule.  Examples may be high speed SerDes on TSMC 45nm, or WiMax cores on 65nm which are targeted at late 2008 / early 2009 prototypes and production.

According to Adam Traidman, President of Chip Estimate, the service will support the current standard IP providers and the customizable product providers.  In the future, Design Centers, Custom Design Service providers and ASIC suppliers may be included in the services offering.


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Oct 16 2007

Intel Developer Forum (IDF) 2007- Still Pushing Technology

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The IDF this year had it fair share of excitement – the announcement of the new microprocessor architecture for the multi-core environment, production on advanced processes and power in addition to performance as a metric. Some of the highlights were:

The introduction of the new Nelaham and Penryn processors on the 45nm process node. The new Penryn processors features a shrink of the 65nm cores with higher performance and operating frequency due to the process size reduction. The Nelaham processors are using a new micro-architecture that features a wider dynamic execution block, a smart cache, an improved digital media interface.

The 45nm process node is the first in volume production using a high-K Hafnium + Metal gate devices. This process claims to offer a >2X the transistor budget per area over 65nm. It features a 20% speed improvement and reduced leakage over the current 65nm MOS process node. The 45nm node is done with all optical litho using 193nm sources.

Intel also introduced a 32nm high speed 200MB+ SRAM. The process was created based on a very extensive test module that included the SRAM product, test modules, and standard, but updated, PCM blocks and devices. The 32nm process utilized immersion litho for several key steps of the manufacturing flow, the rest of the stages are standard dry litho. Both the 45nm and 32nm processes utilized a reduced design rule methodology.

There was a mention in the keynote that in addition to the traditional performance scaling that has been taking place for the server and high performance computing environment, that a new initiative to reduce standby and non-active mode power was being implemented. The goal was static and standby power reduction by a factor of 10x in the next 5 years. This goal is set to address the mobile computing, telecommunication and consumer marketplace.

One of the highly anticipated but surprisingly disappointing aspects of the event was the keynote / discussion with Gordon Moore. Dr. Moore is a well respected, highly intelligent, highly productive member and key founder of the modern semiconductor industry. His IDF presentation was mostly about reminiscing about the early days, which were before most of the audience was out of diapers, and very little discussion of opinions and observations that took place along the way. The perception was, that he was being displayed before the crowd like Punxsutawney Phil on Groundhog’s Day, and if we saw his shadow we got 6 more years of optical lithography. The further indignity was the followup of the talk by the give away “Moore’s Law? t-shirts which were being given out if you visited the partner’s forum. If the keynotes and product announcements had no substantive value or innovation, it might have been a good “diversion? for the crowd. However, with the new process technologies and the new architectures and performance goals, the talk just seemed out of place.


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