Archive for June, 2007

Jun 15 2007

Custom Design and DAC

Published by under General

This years DAC is showing a lot of tools in device level and custom design tools and directions this year. In past years the show has been focusing on SOC, synthesis and P&R. For the new processes, the focus has shifted back to the building blocks – devices, component level physical design, DFM/DFY and power.

The quick one to get out of the way for discussion is power. The big showdown on the show floor between CPF and UPF which was rumored to be aiming to split all the fabs and EDA tool vendors into two camps is not really turning out that way. The actuality on the results is that both have customers using them for designs. Even though the two sides are shouting about who has the biggest numbers, the real decision will be made in the semiconductor customers playing field. As the technology for these two standards are based on implementing known good design techniques that have been historically done manually, the winning solution is most likely be chosen on a chip by chip basis depending on the selection of which mix of power solutions are needed, and how much automation/validation is required for the individual design. There is no real war, just engineering work to be done, and most of the people have better things to do than discuss it.

A lot of the tool vendors in this space actually had good products that appear to be on the right track for the answer (their presentations/booths all had the same foil that showed how they uniquely supported the full set of known power reduction solutions that was invented and used since mid 70′s). In various and multiple parts of the flow for solutions are ArchPro, Sequence, Synopsys, and a whole gang of others that can be found on the lists from the CPF and UPF camps. Once dad gets home from work, and can stop the two kids from fighting by giving them timeouts and sending them to their respective rooms to calm down, the sector should be very effective for the designers.

A big area at the show was the prominence of statistical design. In addition to the traditional big players showing products in the area, there were some small companies showing products that covered a large range of design. These included, but is not limited to, Extreme DA – STA , Solido Design – device level design, and Nanno Solutions – interconnect design.

Other non-front end design tools providers were at the show displaying pretty stable code that supports manufacturing data for variation. This was classified as the DFM/DFY/DF(letter of choice this week to try and present a market differentiation) players who provide business models in the form of tools, services, flow partners and the combo value meal ( but without the large fries, as the sector is health conscious and trying to stay alive). Companies showing in this space included Ponte; Clear Shape; PDF Solutions; Anchor Semiconductor; Blaze DFM; Brion; the big 3 – C, S & M; Magma, SiliconCanvas and probably others. The big guys are all known and positioned in this space, and really don’t need any more discussion, the fabs who are providing processing with the “approved” vs “recommended” tool lists for sign off is all the info any designer needs.

Their were two other players in this area who showed a different spin on the answer – (1) Sagantec, a long time player in the EDA sector, has a DFM fixing/repair tool as they are able to successfully leverage thier compactor/edge mover technology to automatically* repair polygon level problems identified by the tools in the list of Dfx tools (* technology file, context aware rule set, and batteries not included). (2) SoftJin who provides custom software modules for DFM, data translation and manipulation, and most other physical design and synthesis level design subroutines to EDA companies, IDM and Fabless with their own CAD depts and recently Fabs with thier own CAD depts. This is good for the industry, as a lot of the companies are all calling the same “engine” subroutine from their integration kits, we are slowing be relieved of having to see hundreds of pointless benchmark slides and we can have confidence in the accuracy of the answers from the new suppliers as they are all using a common code base inside different bright and shiny wrappers.

It appears, the design world has realized that custom libraries and multiple views are a reality even in a world of licensable IP. This brought out a number of players covering the sector of library creation, characterization and view comparison. Folks in this space are Nangate – Lib creation, characterization and comparison; Fenix DA – view comparison; Altos Design – Characterization, and finally long time market entrants Simucad and Library Technologies who both provide the industry baseline products. There are probably more in this space, the others have their products are part of solution families are not actively promoting them as “point tools” but as part of a large SOC completion picture. The folks at ChipEstimate.com and Design Reuse are continuing to do a good job of providing the industry with an on-line shop and compare feature for licensable IP. As this is a required step for current SOCs, the two companies have done well keeping up with the huge and growing lists as well as providing higher level tools that allow for engineering level comparisons of the offerings, not just lists of existence.

The last area of the show that was showing new stuff for the custom design world was the simulation space. SPICE, RF and AMS simulation are now part of the mainstream flows, so the longtime under appreciated tools are getting the visibility they deserve. These include the two industry standards Synopsys HSPICE and Simucad’s SmartSpice, followed by Berkeley Design Automation, Dolphin Integration, AWR, Ansoft, Agilent, Cadence, Xoomsys, Nascentric, Legend Design Technology, Lynguent, and Mentor.

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