Archive for November, 2006

Nov 27 2006

A Look Back at BACUS 2006 – A Very Lively Show

Published by under General

The SPIE/BACUS Photomask technology conference in Monterey, CA, was very lively this year. Along with the traditional long time faithful attendees, there were a large number of new faces from the EDA-DFM community as well as folks who used to attend the now defunct Advanced Reticle Symposium (ARS).

The conference had it share of imaging, illumination, photoresists, films and substrate materials, repair and inspection papers. A good number of the papers however followed a new trend of DFM, OPC, RET, methodology, tools and design intent validation content. Surprisingly, these papers were being presented by all three sides of the issue – semiconductor companies, wafer/mask fabs and tool providers.

Some of the highlights from conference that seem to directly be of interest to the design community were:

Saratoga Data Systems, which has GDSII file size reducer and a high speed FTP tool. The GDSII product is interesting as it is not a “compression? format where data validation is required to make sure the new file can be “restored? properly, but actuall a reorganization of the eixisting file which makes it not only smaller but still directly usable in the reduced form. They also have introduced a very high FTP protocol that results in many multiples faster data transfer – so remote design teams with centralized server farms running physical verification and MDP/OPC/etc is now actually practical.Soft Jin had poster session about their new distributed “engine? tools that support smart distribution of a core EDA engine (simulation, verification, etc) on multiple machines in a net. One of the cool things about it (that may also limit it’s use) is the fact that to get the performance, the designers have to actually partition and build their designs properly with hierarchy and not create a huge flat blob. Maybe with the performance enhancement that is available with this technology, the RTL designs and P&R engineers will finally follow the rule and do things right.

An interesting poster paper was presented regarding everyone’s favorite topic – ESD. This time, however the issue is not the IC’s but the Masks and the associated carriers. At only 5X images of 65nm and 45nm geometries, ESD strikes that come in the wafer fab line happen on “good? masks, after mask inspection and can destroy real data on the plates. The folks at AMTC reported test results on various carrier materials including some exotic carbon nanotube products to try and reduce this issue. According to Pozzetta Products and Gudeng Precision both suppliers of the reticle carriers, this is one of the top 3 issues brought to their attention by wafer fabs and masks fab world wide.

The big guys – Mentor, Cadence, Synopsys – all had new product roll outs that were shown at the conference and results presented from REAL manufacturing partners and wafer results from fabs and semiconductor companies. I guess the real data and results get saved for the technical conferences, so at DAC we are going to have continue to live off the many bright colors from the product slicks to keep us happy. Cadence , Mentor and Synopsys all have very functional products and results at the show, it is pretty amazing how the practicality of their offerings have non-overlapping results and uses even though the products names are all the same.

As a last highlight – the business side showed continued revenue growth in the mask sector, while the number of units is still stuck at about 700,000/year. The split includes >50% at 0.25um (250nm) or larger and about 2% at 65nm or below. – pc

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