Pallab’s Place

At the 2012 CES conference, there were many IP providers mixed in amongst the many end product companies. These IP providers were showing capabilities as a well as ASSP products targeting the mobile community and handheld products.

The core controller IP providers – Tensilica, ARM, Imagination Technologies and MIPS were all showing their latest scalable blocks targeting higher performance graphics, sound and battery lifetime. These blocks were supported not only be new SDKs but also in reference designs that appeared as early product from the major systems providers.

A change this year was the large number of IP blocks that were incorporated in ASSPs that were shown. Companies such as Nvidia, Broadcom, Samsung, Qualcomm and Marvell were showing thier own versions of these IP blocks, now configured as systems under the larger scope of an architectural licence for these core processors.

Peripherals and interfaces were not left out at the show. The Qi group (Wireless Power Consortium), USB IF, WiSA and Wireless HD, HDMI and Display Port groups had multiple vendors showing both IP and systems/block level solutions. The data rates moved up at the show and most people had the new standards – SATA 3 (6Gbps), USB 3.0 (5Gbps), Thunderbolt (up to 10Gpbs), Display Port 1.3 (5Gbps) in thier products. This has changed the technology node to being 90nm as the largest process size, as the SERDES at this node and below can handle the high speed data in a straight forward manner.

A couple of surprises in the IP is the large number of blocks that stayed at the 1.8v power rails, and did not scale to 1.3v or below. While beneficial for the core logic and state machine portion of the design, the power level has proven to be quite challenging to interface blocks and anything driving large capacitive loads such as cables or connectors.

The FPGA providers were focusing their IP and solutions on the high end display (multiple TV models) and the automotive marketplace. These are both aggregation points for multiple technologies and multiple data bus formats. As a result, the flexibility of the FPGAs logic to be adjusted on a per model basis while providing sub 3Xnm process and performance access is the major driver for the UHD displays and advanced Driver Assist and Automotive Infortainment systems that were shown.

At the IEDM conference in Washington DC this year, the electron device conference moved up from basic layer and element creation for sub 20nm processes and new device technologies. The past couple of years, the conference focused on the ability to create these devices – 3D transistors, FinFets, Graphene devices, double and quad patterned memories – all as can we manufacture them.

This year, the ability to make these devices was second to how do the devices work, how should they be modeled to be compatible with the design community and what are the sensitivities and variability associated with the parametric performance of these devices. The processing capabilities have improved to the point, where these technologies can now be built at production scale for the semiconductor industry. The big question is – can designs be created that can simultaneously take advantage of their new performance characteristics while compensating for the challenges of these devices and their differences from the traditional MOS switch?

To address this question, about 30% of the sessions were focused on the device modeling and the actual current transport mechanism in the new structures. These included, the associated variability in gain, on/off resistance, and the transconductance and other basic device parameters. These were both shown from empirical data collected and from TCAD and mathematical models. These models were used, and shown in the joint circuit design session, as part of the advanced applications sessions.

The models were not just for single devices, but there were tutorials and findings on MEMS, Sensors, Biodevices, Energy Harvesting Devices, and high power (up to 6.5Kv and 2500A) solid state transistors also. These technologies, more so than traditional lithographic scaling, are becoming the new drivers for advanced technologies. The capabilities of the solid state devices has now moved on from just smaller/faster to being new capabilities, power aware and context aware.

As a result, the understanding of how these mechanical and biological interface devices as well as power handing devices – all of which are not handled by traditional RTL and digital verilog descriptions – will be the new basis for broad appeal design moving forward. The EDA community has not really been addressing this as yet, as it is not algorithmically derivative of current solutions tools in the market. These new markets are currently being addressed by TCAD tools, mathematical and physics based modeling tools and in-house created tools as has long been the mainstay of the analog/specialty design marketplace. As things move forward, the mainstream EDA community has to address these directions and bring solutions or the in-house ad-hoc solutions that are built for a specific process will once again dominate the design industry as it did in the 60′s-70′s pre-EDA gen 1.

ARM just introduced a new high performance, low power, graphics core that can be instanced as multicore for up to eight instances as a GPU in the Midgard architecture for sub 32nm process. The Midgard architecture now has the T604 and T658 as multi-core visual computing cores. The two main features of the new core are the ability to scale to 8 shader and arithmetic pipes in one core and an extensive API library that allows for commonality of code across multiple platforms (mobile to large screen TV).

ARM Mali T658 GPU Architecure

The multi-core architecture required a new cache system to provide increased coherency for the 8 cores. They are grouped as a single cache shared with 4 shader cores sharing a memory management unit and an AMBA interface. The core now supports an integrated automatic load balancer for the cores. The target mobile applications is superphones in either a quad or octal configuration with the “big-little” CPU cores the Cortex-A15/A7 pairing.

The shader set supports graphics APIs – Direct X10 & X11, OpenGL, OpenVG and computer APIs – OpenCL, Renderscript and DirectCompute. The APIs have already been incorporated in to several development systems including the game development tools from Unity.

As the IP block is targeted for implementation in licensee SOCs, multi-stream data access, incorporation and support of a hypervisor, vitalization of the memory access and multi-display drive are currently not part of the IP block, but are being developed the partners in the ARM ecosystems for vertical market specific needs.

PC

The IEEE Nanotechnology Council is holding a half day seminar on photonics on Tues Nov 15 in Santa Clara. (info at http://www.ieee.org.nano) The area of photonics is quite varied these days and the program is addressing 4 key areas of the technology.

Opening speaker Dr. Hughes Matras from CEA Leti (Grenoble, FR) will be discussing 3D ICs and chip-to-chip photonics interconnects. They will be presenting results and goals for thier ongoing research in the space. These parts are targeted for both Si based photonic circuits – logic to logic and logic to memory.

The second speaker is Dr. Chanming Su of Bruker-Nano. Dr. Su has create a fast scan Atomic Force Microscope which now enables single digit nanometer resolution metrology at practical quality assurance and debug speeds. One of the major challenges of nanotechnology is the imaging of the geometries in question. A second challenge is to verify that these sub-resolution features and the resulting devices are created properly. The presentation will review the technology behind the Fast Scan AFM as well as capabilities of the tool in production use.

The next speaker will be Dr. Hakaru Mizoguchi of Gigaphoton. He will be discussion the advances in EVU lithography through their development of a new high power EUV source. The new source is based on an ionization system for the liquid Sn droplet atomizier. The final speaker is Dr. Xiang Zhang of UCB. He will be presenting on solid state lasers and limits on diffraction grading and other optical elements in solid state light paths. These products are a critical part of high speed communication.

After the speakers presentation, Ed Sperling of Semiconductor Manufacturing & Design (www.semimd.com) will lead the panelists in a discussion of future directions and challenges in integrated photonics and the process technologies they will be using. Registration for the event is available on-line at www.ieee.org/nano and admission is also available at the door for the event. The event is being held at the Texas Instruments Conference Center in Santa Clara. The center was formally the National Semiconductor Conference Center and runs from 12noon – 5pm on 11/15. Lunch is included and parking is free.

The 2011 ARM Techcon was well attended and busy this year. The technical sessions were rightfully quite packed as the topics being presented by ARM and it is many partners was low on product advertising and high on technical content – a rarity for many of today’s events. The conference addresses a diverse client base – IP creators/providers, SOC developers, FPGA users that integrate the cores, and systems designers that use both custom and standard products that incorporate the ARM cores. In past years, the communities were tightly integrated, this years event, chose to separate the two groups (chips and systems) segregating the “chip” folks to the “kids table and being out of sight/sound of the adults” and the “systems” folks to the “grown ups” who got the “big table in the main room”.

The challenge that results, is that attendees who are doing SOC design for a specific application, now need to attend all three days, but two of the days do not discuss the context of the architecture, test, programming and performance optimization that reviewed on the Systems days, The attendees building systems now also have to attend all three days to get the technology overviews, low power techniques, reliability and interface details from the chip day to understand how to take advantage of these features in their FPGA and board level implementations.

There were a number of design tradeoff sessions that had new design solutions such as the SiTime MEMS resonator which in addition to being a stacked die integratable solution, also allows for the elimination of PLLs in the SOC design and the timing issues associated with the jitter in traditional PLL based clock distribution designs. This is becoming more critical as additional sensors are being used in these multi-core systems, so temperature compensation and data converter stability have increased impact on the overall performance. The results are fsec jitter levels on a 100Mhz clock.

The systems day included an overview of ARM itself and had a nice tradeoff comparison of the ARM vs Cortex processors, and the 16, 32 and 64 bit instruction sets, applications, and programing requirements for the various applications. This discussion included the multi-core architectures and pipeline designs of these cores and the associated AMBA system IP / Mali Media IP.

An overall theme was that the ARM IP was designed for minimizing power consumption while providing the highest performance/power ratio in the industry. This has allowed the IP to be used in literally Billions of end products shipped, since the company was formed in 1990. The product line was shown to be addressing the shift in market need from simple control of an application to being a main compute processor for mobile multi-media data consumption.

PC

In a recent discussion with Fawzi Behmann, we reviewed the state of the Power Architecture, which is now in its 20th year. The processor was started as reasearch in 1977, and then became a a standalone product (the 68000 processor) in 1979. The Power Architecture was put into SoCs in the early 1990′s and was introduced as a multicore with virtualization architecture in 2001. The current version of the processor – the Power7 is the compute engine behind the IBM Power7-Blue Water HPC and the Blue Gene / Q. The group Power.org put together the Power ISA in 2005 that created a spec for the product and specified the supply chain. In 2010, they released version 2.06B of the spec, which dealt with multicore, virtualization, energy management and reliability of the design and cores. The core is now able to take advantage of new operating systems and appellations thanks to new SDKs that have been developed. They are moving to run OpenCL and Android has been ported to PowerPC along with the other platforms. This allows for embedded applications to get an optimized OS, and the code is available in source form, and proprietary kernals can be developed. The graphic that follows shows the current roadmap for processors and cores.

Power Architecture Roadmap

One of the new applications of the part which has dominated space use, medical instruments and automotive, telecom, compute/analytic applications is natural language processing. This is not the same as the regular expression processing for policy decisions, rather, it is targeted at health care and medical record processing. The engine can process upwards of 200M pages/sec of EHR. These new applications are starting to take advantage of the transactional memory design in the Power7 which is optimized for multi-core processing. The SoC design for the cores is a hardware/software co-design function. The designs are captured using Rational. And then a flow (as shown in the following figure) is used to create the design using EDA tools from Synopsys, Cadence and Mentor for the hardware design. The design is a true 64 bit with full 32 bit subsets.

Hardware/Software Collaborative Development

To enable new development and increase embedded applications, Power.org has worked to simplify the licensing of the technology. The license model now includes: IBM Power Architecture Licensing Program – Lowering Barrier for Developers (a) “No-barriers” license for Power 405 (no standard access fee) (b) Multi-use agreement for Power 405, 460 and 470 for 5-years (c) Synopsys University program for Power 405 member access for new applications (d) VAR agreement with C*Core. These licenses have additional provisions for China and as a result they are experiencing high growth in multiple markets.

On Nov 3 & 4, 2011, the Center for E3S of  the EECS department is holding their second annual conference at the UC Berkeley campus.  This year’s event spans 2 days and has 19 confirmed speakers following a keynote to be presented by Dan Hutcheson of VLSI Research Inc .  This years symposium will cover a range of topics including:

The center’s chair Dr. Eli  Yablonovitch will be speaking and showing off research activities in the group.  The center is focusing on the challenges of lowering the operating voltage of electronics and electronic systems and addressing the growing power that is being consumed by the aggregated IT infrastruture and connectivity that is pervasive in today’s society.  The E3S Center is responding to the challenge under the following charter:

“The Center for Energy Efficient Electronics Science (E³S) has been established to:

• Open a new energy efficiency frontier in information technology by developing transformative science and technology that reduce energy consumption in electronic systems by orders of magnitude.
• Inspire and train a diverse generation of scientists, engineers, and technicians that applies this new science and technology to benefit society.”

based on the quality and diversity of speakers, this events is shaping up to be the premier low power event on the west coast this year.  Information on the conference and registration is available at:

http://www.e3s-center.org/events/11/sym2011-home.htm/

Discounted early registration is available on the site through October 7.

PC

At the 2011 SPIE masking conference, known as BACUS, we had a chance to meet with and talk to Aki Fujimura of D2S, Inc about his company’s new product offering. The new platform is an interactive masking workstation that allows for simultaneous optimization of lithographic patterning for BOTH mask and the resulting wafer image.

The integrated software / workstation platform was created to address the discontinuity that has arrived at the sub-80nm (on mask feature size) / sub-20nm (on wafer feature size) nodes.The system works by having mask designers target highly critical areas and/or highly repetitive patterns up to 300umX300um (on mask). TrueMask DS allows the user to interactively trade-off the mask shot count and mask manufacturing margin with wafer manufacturing margin down to a resolution of 0.1nm on mask. The system also features Litho aerial simulation which helps feed the reduced interpretation time from running the 5umx5um (on wafer) object analysis. The graphic shows screen images that result from the various types of simulation.

Modeling results from TrueMask Mask-Wafer Double Simulation

The system helps bend the curve on mask costs. As current multi-million dollar mask cost explode due to multiple patterning and the need for complex shapes, this model based approach is targeting up to 25% cost savings for processing the shape set that is anticipated for the 15nm and below nodes. There is a corresponding shortening of the schedule along with the cost savings for the materials. As the system support eBeam sources, the system can simulate rectilinear, overlapping and in the future, variable shaped beam sources.

At 20nm feature size, the amount of OPC (Optical Pattern Correction) and SRF (Sub-Resolution Features) that is required to correctly represent the layout feature is very high. The features require many complex mask shapes, which may not be repeated based on context over large reach areas. The tool set reads GDSII and OASIS data and can interface with SEM for inspection of both mask and wafer patterns.

At the Flash Memory Summit, we had a chance to meet with David Eggleston who is the CEO of Unity Semi.  The RRAM company has recently re-targeted its business model.  The new model is based on a traditional IP licensing structure which includes process, design and scalability licenses.  The IP is based in part on their 120 patents for the CMOX cell technology that have been granted, and the over 100 that are in process.

The current portfolio of IP includes cells, product and macro designs, architectures, and application support (interface design, SDKs, etc).  They have announced one licensee which is Micron Technology which announced a 2 year JDP starting in 2010.

Currently the company is receiving 1/3 of its revenue from product sales and design/process services with their fab lite model.  They are targeting fabs, IDM and ODMs as licensing partners.

The company was formed in 2002, and created the first CMOX cells in 2004.  The cells are available in single bit (SLC), dual bit (MLC) and triple bit (TLC) data architectures. Backers Seagate and Micron are driving the technology for cloud based applications of active memory with a new optimization point for capacity, performance, ease of use and low cost.

The page based memory are moving towards a cents/GB cost with 1TB Capacity, and performance in the 500Mb/s R & 200Mb/s W range.

PC

At the Flash Memory Summit in August, there was a non-Flash session dealing with new memory technologies.  It covered both RRAM and MRAM also known as Resistive RAM and Magnetic RAM technologies.

The Magnetic RAM (MRAM) arena also presented an technology update.  The updates were from Avalanche Tech, Corcus, Everspin, MagSil and new startup Spin Transfer Technology.  Avalanche Tech lead things off with an update of their 3rd Generation MRAM product which is a spin programable memory.  The structure is best fit att addressing the SLC NOR and embedded SLC marketplace since it has a fast switching time (under 1ns) and is 3D stack-able to approach the high densities.  The product can also be configured to DRAM type applications, which make it a good universal memory product for both the controller interface and product store of Enterprise class SSDs.

Crocus discussed some of the details on their new JDP with a Russian Nanoelectronics Corp which will be investing $300M to bring up a 12″ fab for the technology.  The technology is base on an MLU concept (Magnetic Logic Unit) block that has it’s memory element from a TAS (Thermaly Assisted Switching) technology.  The MLU implements a “native XOR” function in the cell design.  The new strucutre is a self differential cell that supports high temperature operation and assembly (200C operation).  The Crocus designs are applicable for NAND replacement, MLC applications, and both CAM/TCAM uses.

MagSil, a seven year old fabless startup gave an overview of thier technology which has been designed in 180nm and is extensible to 18nm without physics changes.  They have been concentrating on solving the field issues related to the switching of magnetic films and have now developed solutions that are compatible with both Copper (Cu) and Aluminum (Al) interconnect solutions.  They are expecting sample parts to be available in the 2013 time frame.

A new entry to the MRAM arena is Spin Transfer Technology (STT) which described an Orthoganal Spin Transfer (OST) technology.  This type of MRAM has a structured, deterministic switching torque.  This characteristic can be used to drive for instant on-instant off memory applications for the mobile marketplace.  The technology, tested to the block level so far, has a 99% probability of <1ns switching between states.

The last update was from Everspin, which is the only company that is commercially shipping MRAM products to applications.  Their customers include Airbus and BMW, and theiy have shipped 3M pcs to date.  Thier fab light model includes thier BEOL fab for the MRAM using base layers built by commercial CMOS foundry.  They currently have over 70 product SKUs and their main use is in SPI SRAM replacement.  The durability of the product is proven by the application from Airbus which is the memory for the blackbox.