Pallab’s Place

I recently had a chance to have a conversation with Judy Priest of Cisco about some of the design and packaging issues for accepting and qualifying new SOCs for high speed networking applications.  Historically, the high end network packages were being designed and selected as both heat spreaders and pitch spreaders between the IC pad pitch and those of the interconnect on the PCB.  This has changed in a current era of board level signals >20GHz and power supplies below 1V.

In order to meet these performance specifications, these networking systems have become very large die (around 20mm/side) and these are in packages occupying 55mm/side.  These can be either single die systems, multiple die arranged in a planar fashion in a single package cavity or thinned and stacked die in one package.  For single die systems, the package configuration has a great deal of influence on the placement and separation of voltage islands, and global placement of power down blocks and functions as dictated by the bond wire and board level signal integrity requirements. For multi-die systems, these same issues as well as data pattern based thermal management inside the package environment is also a key design element that needs to be fed back to the IC design as a floor plan constraint.  Stacked die (traditional, not TSV based) and very large single die have these same design constraints in addition to package and die / package warpage and material stress issues.  The warpage and stress that is in the package is variable based on the density and material used for the different styles of current generation HiK and Lead free packages.  These two effects can cause differences in the leakage power and timing  performance of the die since it mechanically changes the planarity of the silicon substrate.

Most high speed networking products are being deigned for 10yr+ die and package/bond reliability.  This brings back to the chip design and architecture level the final assembly criteria of die thickness, pad size and reliability for wire or bump bond, shock survivability from a drop test and wave solder/post assembly high temperature processing (a known susceptibility for technologies such as PCM memory).

Judy will be discussing these and more details about design tradeoffs between package and die at the MEPTEC Chip to System Symposium (http://www.meptec.org/meptecfromchipto.html) being held in San Jose at the end of February.  With the invasive nature of the need for high speed connectivity in most of today’s systems and SOCs, is driving package interaction from a niche issue to being a mainstream concern very quickly.

PC

One of the key components of the audio systems (amplifers, guitars, mixers, etc) are the knobs and sliders.  Continuing their long history in the potentiometer business, they are re-issuing classic products and bringing out new products for new applications.

On the classic side, they have reissued the Model 82 Vintage Premium Guitar Potentiometer.  The new pot is now RoHS compliant, has the same low noise performance as the original from 1977 and features a 100,000 turn rotational life.  This is the classic guitar and bass tuning knob used with Seymore Duncan pickups on Fender Signature Series guitars.

On the new products side, they have added new RoHS compliant Resistive Sliders for the audio and broadcast mixer market.  These sliders are motorized with built in servos and are available with and without the built-in data converter.  They feature a long life carbon element and support either PC terminals or a snap-in connector option.

New products in the low noise, RoHS compliant line are manual sliders for mixing boards, and for solid state and tube amplifiers are forth coming.  All of these parts are designed to maximize the Quality and Reliability.  The targeted life cycle in use at the application is 20+yrs, for this reason, testing and quality assurance are hallmarks of these parts.

They are in the process of developing new potentiometer technology based on non-contact magnetic materials.

PC

This years NAMM show, and some carryover from CES, was heavily focused on making use of the advanced processing & storage capabilities available in very low power form factors.  The result was Generation 3.0 of advanced sampling and modeling systems that now using the full data bandwidth and signal handling features that are available in standard components for both the consumer and industrial marketplace.

The Generation 1.0 was started back in the 1960’s with the analog based sampling, effects and modulated playback that was defined by the Moog Synthesizer invented in 1964 by Bob Moog.  To honor this starting place, the NAMM show and The Bob Moog Foundation displayed some key artifacts, equipment and material from the Waves of Inspiration: The Legacy of Moog exhibition which is running from August 29, 2009–April 30, 2010, at the Museum of Making Music’s facilities in Carlsbad, California.

The Generation 2.0 was the long cycle, still on-going, of sampled music and sampled MIDI/VST instruments that ranged from rudimentary low resolution data to high accuracy single note and single sound samples at mid level data rates. These digital solutions were targeted at moderate capability portable and stage devices, based on power limitations, and high quality capability has been reserved for desktop/studio platforms.  These generation 2.0 solutions were still prevalent in existing digital products from Yamaha, Roland, Sony hardware and software from Garritan, Calkwalk, Native Instruments, and Garage Band.  Yamaha introduced a MIDI audio-visual device designed by renowned artist Toshio Iwai.  The device is shown in the following photo, and is an interactive art piece that has 256 programmable LED buttons that can display patterns and play music in the modes of up to 64 simultaneous samples at once.  The features and SD card and MIDI interfaces and utilizes dual 32 bit embedded processors on a custom (linux based) OS.  The music can be programmed as full songs, or in draw mode, fully interactive with sounds based on touch interface with the LED keys.

Tenori-on Orange

The Generation 3.0 is now starting and is characterized as utilizing the full capability of 2010 era mobile and studio digital processing as well as “musical sampling”.  “Musical Sampling” is the concept and the capture of instrument sounds and effects, NOT on a standalone note basis, but in context of other notes and chords, and materials of the instruments.  The Generation 3.0 has been in place for a little while, promoted by Line6 with their DSP based solid state modeling amps which recreate historic tube amplifiers, and Roland with their V-Series of instruments.  Roland continued to expand thier V-series instruments with a new electronic drum kit and components, a new drum pad (the Octapad). a V-series combo piano/organ, and a new low priced and simple interface voice processor (VP-7), in addition to their existing keyboard line.  The V-line of equipment is migrating from stored samples as the playback method, rather they have created continuous time and multi-note correlated models for the notes, chords and phrases being played back.  Following this technology, the VP-7 is small effects box that takes a microphone input (through an XLR connection) and a MIDI interface from a keyboard, and then generates vocal harmonies as either female choir, kids choir, Gregorian choir, jazz scat, duet or trio in real time, for use in live performance environments, based on both the notes sung by the vocalist and the chords played on the keyboard.  Previously, these products were only available as studio products in the several thousand dollar range, the VP-7 is a small form factor accessory in the several hundred dollar range.  A demo is available at http://www.rolandus.com/products/productdetails.php?ProductId=1062

Yamaha also has introduced a new line of stage pianos and electronic drum systems.  These incorporate phrase and context based samples as well as new materials.  The drums have new electronic heads that are both more responsive and sensitive.  The keyboards feature new weighted keys that are almost indistinguishable from those used on their concert grand acoustic pianos.  The keyboards also supports full modeling of the hammers, pedals, and both adjacent and non-adjacent keys being used simultaneously and the harmonics generation on the sound board.

The drop in price, capacity and performance for external HDDs has made them the new preferred distribution format for the sampled and modeled instruments.  The availability of this format (typically a 60GB-1.2TB distribution) has allowed for a new form of sampled data.  The resolution is higher at 24bits/96K or 24bits/192K sampling.  In addition to traditional “note” based information, context, phrase based, “grove based”, and equipment options are now part of the environment.  On the equipment side, it is not only effects and amp modeling, but on band instruments there are also options.  On the band instrument side it includes wood and metal mutes for brass instruments, different mouthpiece types for woodwinds and both current and classic drum kits and cymbals.  PG Music’s Band in a Box product is shipped on a 160GB USB HDD for their complete “chord based” music samples in compressed format.  Their full “audiophile” lossless product has the samples in an uncompressed format that is suitable for professional studio application is shipped on a 1.5TB USB HDD.

Following this trend toward more realistic sound, for percussion Sonic Reality has introduced “Epik Drums – a Ken Scott Collection”. Ken is the legendary British recording engineer and producer who recorded The Beatles, David Bowie, Elton John, Supertramp, Pink Floyd, Jeff Beck, Mahavishnu Orchestra, Dixie Dregs, Devo, Lou Reed, America and many other iconic artists.  The new virtual instrument plug-in contains 80GB of 24 bit drum samples recorded in multi-track as a combination of audio grooves and MIDI kits.  These samples were recorded from authentic historic drum kits and configurations by top drummers Billy Cobham, Bob Siebenberg, Terry Bozzio, Woody Woodmansey and Rod Morganstein as they played on the original albums.

Ken Scott - Epik Drum

To utilize these new samples and virtual instruments, the folks at Eigenlabs (UK) have created a new performance oriented instrument called the Eigenharp.  It is available in three models the Alpha (top of the line, largest, professional market), the Pico (smallest, consumer product) and the new Tau (middle).  The instrument has patented 3D position sensitive keys, pressure sensitive resistive strip controllers, and a breath pipe controller that act as the programmable and playback surface for the device.  The three models differ in the number and type of control keys (standard and percussive), number of strip controllers and finishes.  Using the instrument the musican can play and record loops, change scale and key, transpose, alter tempo, program beats, create arrangements, switch and layer multiple sounds, all while the musician is performing live on stage.  A photo of the Eigenharp Alpha follows.

Eigenharp Alpha

Another instrument that is getting new modeling capabilities are the guitar and bass.  Brown’s Guitar Factory (Minnesota) has been building custom electric basses for several years.  Recently they created a Kahler bass tremolo system with acoustic and MIDI saddles that can track and sound as accurate as the best performing keyboard synthesizers on the market. They are offering this as a conversion kit and as a 4 string acoustic-MIDI electric bass.  It can be played as a standard bass or through a modeling system to act as a full synthesize controller.  On the guitar side, Gibson introduced thier 3rd generation auto-tuning guitar – The Dusk Tiger.  Once again, based on the Les Paul solid body guitar, the auto-tuning system features improved PZT controls for the tuning heads, a new re-chargeable battery configuration, and a modeling systems that can be downloaded into the guitar.  Using the supplied software, you can program the guitar to different tuning modes, to sound like different pickups and guitar models.  The new control knob also supports several standard classic guitar models as standard loaded in the guitar.  As in previous models, the guitar is targeted as a stage performance instrument, so at playback, just a standard guitar amp is used through the 1/4″ jack and it is played normally.

The last area that saw improvement in dynamic range and sonic reproduction was in the area of headphones and earphones.  Ultimate Ears (now a Logitech Company) has been making in-ear custom monitors for touring musicians and sound engineers for over 12 years.  Using advanced sound guide design, custom cross over circuits, and state of the art COTS speakers, they were presenting custom molded duel ear monitors with 2 to 6 speakers, including sub-woofers.  The custom ear molds insure that there is sufficient sound isolation from the ambient environment to allow the performers to hear the playback they need during live stage performances.  These in-ear monitor systems feature a frequency response of 20hz-18KHz and input sensitivities up to 124dB @ 1mW, and 26dB of noise isolation.  These are typically professional level products, however their intro level product is a dual speaker system that is price compatible with most DJ level and home studio over the ear headphones.

On the consumer side there several new in-ear speaker systems from Monster Cable.  Based on their experiences with the Dr. Dre “Beats” headphones from Monster Cable,  Erin Davis (Miles Davis’s son) and Vince Wilburn Jr (Miles Davis’s nephew) approached Noel Lee about making a headphone for the Jazz marketplace.

Erin Davis

Vince Wilburn Jr.

Working with the group at Monster they created the Miles Davis Tribute in-ear speakers that are derivative of the Turbine in-ear speakers released in 2009.  In order to test and qualify the product, in addition to standard testing, they also sought feedback from artists who have been in Jazz for a long time and some of whom played with Miles.  One of the people reviewing the product was Lenny White who played with Miles on the seminal album “Bitches Brew”, is the drummer for the Jazz-Fusion defining group Return to Forever, and has recorded and played with artists from just about every genre.

Lenny White

In addition., to the Miles Davis in-ear speakers, Monster also released the Turbine Pro Copper product with is an upgraded version of the Turbine in-ear speakers featuring enhanced bass, and a faster response time for improved clarity at the high frequencies.  The Pro product is more of studio class / audiophile product than the Turbine speakers.  The new ear buds improve sound isolation, so the in-ear product behaves in the same class as a traditional over the ear product.

The summary from the show was that now that processing power is available in mobile and low power platforms, the environment to musically capture, playback and monitor high performance audio, based on a digital signal path, is at levels nearly inpercetibly different from traditional analog (strings, woodwind and brass) instruments.  This adds a new dimension to the ability to distribute music and adds another dimension of creativity to the traditional musician to explore new music and styles anywhere / anytime.

Peter Chatterjee and Pallab Chatterjee

Recently there have been several blogs, emails and articles from people talking about benchmarks in DRC/LVS/RCE/Appl Rules (general class of Physical Verification or PV tools) and some of those were run using runsets from vendor A on tools from vendor B.  These benchmarks were created to show “whose’s tool is the biggest and best” in the continued posturing war between EDA vendors.   As a result of this ritualistic posturing and “fanning of their plumage (benchmarks)” a large portion of the design community cannot correctly identify use models or selection criteria for these tools.

To help out in this situation, here are some basic information to understand and some questions to ask when reviewing information or statistics on PV tools.  For the sake of simplicity, I will be discussing issues with respect to Design Rule Checking (DRC), there are similar but different guidlines for LVS, ERC, RCE, and Application Rules Checking.

The first thing to understand is that there are several categories of design rules available from a wafer fab – (A) the basic structure rules, (B) yield and reliability rules, ( C) device operation rules, (D) suggested design rules, (E) optional design rules, (F) I/O rules, (G) power rules and (H) DFM/Litho rules.  Design rule sets for larger geometry processes (>0.35um)could typically be described in under 250 rules, most modern processes have upwards of 2000 rules a large portion of which are context based.  Signoff qualification for the right to release a design to a wafer fab usually includes passing ALL of the rules (A-H) being released by the fab.  The runset(s) are qualified on test data & real designs, validated for a specific version and mode of BOTH the parser and code, and released for specific minimum hardware platforms/configurations and operating systems.

To put the qualification effort into practical terms, based on the creation of several hundred PV runsets I have created/been involved with the creation of: for a typical layer on a 40nm process (e.g. diffusion or Metal 1) the basic design rules include minimum width and size, if bends are allowed, and parallel line spacing to the same layer or adjacent layers and use only simple boolean operations and “generation 1″ verification rules.  These “generation 1″ rules have existed since Maskcap/GPL days (1970’s) and are supported by pretty much every tool on the market.  These rules take about 4 hours each to validate between the creation of the test case, running it on the software, verifying the results as only errors being flagged, and getting signoff from CAD / design / process engineering and moving the code to a releasable area.,

The balance of the rules tend to be coded with syntax that is described in the EDA companies documentation about the function inside of their tool, but the implementation and algorithms used are different in each tool.  Hence the operation, flag location and aspects of checked objects (projections, vertices, edges) may be different in different modes (flat, hierarchical, dynamic) as well as in different tools.  These rules tend to have test cases that are in blocks cut from real designs, rather than created from standalone test cases.  Hence, these rules as coded in the complete runset take about 6 hours each for the validation loop.  For a typical 40nm process the 2000 rules consume about 11,200 man hours to validate for wafer release/signoff quality approval for the first software tool, and about 60% of that (6,720 man hours) for subsequent tools, as the test cases are already done.

With this extent of an effort behind the release of a runset for use, for a particular tool, implies there is a certain degree of difficulty and subtlety in the coding and construction of the runsets and also the mode of the PV tool, at runtime. [The complexity of this task is what is prompting the “unified  parser” methodology of TSMC’s iDRC program.  This is a vendor independent description language for the topological rules in the process.  At this time, the iDRC runsets do not provide for vendor optimized operation, and currently produce different results (number of real and false errors being flagged) from different tools when the results are compared in both flat and hierarchical modes.] This effort for the qualification of runsets, has led most EDA companies to run benchmarks for customers on their “preferred process” and existing designs, using “golden runsets” that are already qualified for the process, but area typically for other vendors tools.

When the runsets are used, the PV tools have a first step which is a parser that identifies where the input and output files are placed, which cell and level of hierarchy to start on, and verifies that commands in the runset have the right syntax and are interpretable by the core PV program.  It is in this step, that the vendors “run” each other’s files.  The results of the parser are a runset and associated files that guide the executable portion of the PV tool to do its job.  Lines of code in the runset that are not compatible with the PV tool are flagged with “warnings” and “non-fatal errors” and ignored at runtime.  In the “cross running” of runsets it is not unusual for a 2000 rule check file to have less than 750 “equivalent” checks that preformed in the other vendors tool.  The parser will also indicate issues such as which mode the tool is run in, and if associated support files are present.  In the absence of these files in the proper syntax/format, most of the PV tools default back to FLAT mode.  In flat mode, every polygon in the design is checked uniquely, rather then being checked inside of a cell so “2 input nand gate” is checked over and over for every instance, rather than being checked just once.  For a typical 65nm to 40nm design with 100M+ devices, it is guaranteed to crash any single CPU computer with up to 64G of memory, due to file size when checked in FLAT mode.

The parser also sets up the parallel processing and distributed computing modes for the PV tool.  As each vendors tool tends to launch differently and access the license server differently, when you run someone else’s runset, then the PV tools usually default back to a single machine (1 -2 CPU, and up to 8 cores/threads, license availability permiting) under an SMP environment.

When you compare the benchmarks or run runsets from one tool on another, you have make sure of the following:

(A) how many rules are being checked.

(B) if the parser and the warnings CHANGED any rules or options by substituting items that may change the context and intent of the rules.

( C) what mode the tool is running and on what cells the checks are being performed.

(D) what the IT infrastructure for the PV tools is set for when operated in recommended mode (how many CPUs, how much RAM, local or remote disk store, interactive or non-graphic display mode, licensing access and job submit methodology, etc)

(E) that the input file format is the same (launched from inside a tool on an internal database format vs from a GDSII or OA file)

(F) format and number of output files created.

These constitute the majority of the issues in comparing the runtime benchmark numbers between vendor tools.  The useful information for a design release is actually NOT the runtime numbers, as they tend to be less than 10% of the Physical Verification cycle.  The key issues on comparing the tools should be: (1) what is the signoff criteria from the FAB for release of a design to manufacturing – This is the main criteria, and (2) which has the most interpretable error flags for identifying not only what is wrong, but leads to how it should be fixed.

Having a tool that is fast at generating lots of flags, both REAL and FALSE and having to weed through them, is actually worse than a tool with 10% longer runtime, that has NO or MINIMUM False errors, and the context description of the rule so a fix can be determined.

PC

The CES big product trends were focused on 3D and tablet devices.  There were several component and design trends that were driving these devices.   Most of the products on the show floor were using standard products as components with customization either with programmable logic devices (e.g. FPGAs) or through specialized firmware/software.  There were very few new custom chips or ASICs in this year’s products.

On the TV side, there were a number of design changes to the 2D products.  The biggest feature changes were the shift to higher scan rates – 120hz and 240hz for LCDs, 600Hz for Plasma, a shift to LED and low power back light, and also adding internet connectivity with embedded application.  In order to support the higher scan rates, the drivers are utilizing smaller process geometries and more memory, To support the new backlight schemes, there are new standard product control chips which have been designed to target the new Energy Star requirements on the sets/ The addition of internet connectivity and the resulting application capability (VOD movies, You Tube, Photo sites, web search, Hulu, etc)   This requires both an operating system (Linux derivatives ) and a local compute engine.  These processors are dominated by the ARM, ARC and MIPS cores which are being embedded into the control electronics.  So far, none of the new 2D sets have incorporated higher speed connectivity that is found in HDMI 1.4 or higher capacity/bandwidth storage that is found in USB3.0 or SD XC interfaces.

Increased reliability, reduced power and cost was also featured in both TV and radio products.  Imagination Technology showed several IP products based on their META processor and thier frequency agile radio technology.  These appears in new radio products from PURE, and support over the air radio in the format for several countries as well as internet radio with search and apps such as facebook/twitter access.  On the TV side, ESS Technology has introduced their first full silicon Multi-standard CMOS TV tuner called the Radix.  The tuner is a monolithic replacement for traditional can tuners.  The product is price competitive with those tuners due to advanced design methods that eliminate the need for manual or post assembly calibration of the tuners and by using low cost foundry processes.  Their new format agile tuner, features fast channel selection and  employs a number of  patented circuit techniques for handling the continuous time signal path, and not having data dependent signal corruption.  The part features SNR specs on the same level as the can tuners while the packaging and power profiles provide increased immunity to interference from the back light and remote control circuitry.  The parts are available in Q1 ‘10 and feature a 400mW operating power over 48-10005MHz when using a 40-QFN package.

Continuing the embedded processors for apps trend, connectivity is now making its way into health care products (such as the TABSAFE) and the Mommy Tech (locator) products.  The Continua health alliance is promoting (along with Freescale) the Zigbee protocol for data between as base station/pc and a mobile medical device such as the Nonin Pulse-oximeter, or a blood pressure cuff.  The Tabsafe product is an evolution of an existing product from the clinical community that is now being made available for the home marketplace with data logging to a computer and/or your doctor on daily medication dispensing and dosage.  With the new connectivity, the physician can now modify a dose rate and pattern automatically to insure conformance on the dispensing of the medication.

Question:  How would you insert 5 square millimeter chip through a needle?
Answer:  By stretching it into a thin string of 5 square millimeter chips.

Well, that is what I thought when I heard about SemiPack’s sub-micron multi-chip module assembly (www.semipack.com) at the BIOMEDevice conference held at San Jose Convention Center last week.  It appears that SemiPack has developed a manufacturing process to grind a wafer down to thin sheet and by slicing this thin sheet into thin strips, they can create a string of chips.  By applying this technique, they have recently developed 2 mm thin multi-layer silicon substrate for multi-chip module assembly for creating intravenous blood composition monitoring device.

Thus, it seems perceivable that we will be able to create active SOC laid out in a long strip to create monolithic BIOMED electronic string for minimally invasive and intravenous applications.  Perhaps, we may soon be able to attach MEMS flagella to make it propel along Intravenous network to monitor and supplement biological host system (http://www.ncbi.nlm.nih.gov/bookshelf/br.fcgi?book=mboc4&part=A2879&rendertype=figure&id=A2879).

This may sound far out science fiction, but this trend seems inevitable.   Dr. Deborah Schenberger explained during her presentation at the BIOMEDevice Forum that “Cardiovascular disease alone is claiming 850 thousand American lives each year.”  This is driving the frantic race for innovation on healthcare industry from medical diagnostic device companies to personalized genomic pharmaceutical companies.   For example, array of tiny needles on medical “Skin Patches” deliver slow-release medication through person’s skin (no more big scary syringes with long sharp needles) while Microfluidics could be placed deep within patient’s brain to allow precise delivery of designer drugs directly into their spinal cord.   It seemed, the whole industry is turning biological in this conference.

So, is this the beginning of the end for semiconductor industry yielding its ways to biological industry?  Not so, says the panelists of biomedical industry experts in Personalized Medicines.   Dr. Thomas Quertermous at Stanford University School of Medicine explains that the collaboration of multidisciplinary industry is more crucial now than ever for improving the efficiencies and efficacies of current healthcare industry for exponential growth and success it deserves.

Personalized medicine means massive information gathering to find customized solutions for each individuals in their own unique environments.   This requires all kinds of sensors and electronics – massive storage space for example to hold all these information captured from every facets of life.   And ultimately, it necessitates the need for even more computing power to efficiently sort through these massive data within acceptable time, space, and energy.   These calls for consolidation of all our engineering talents and scientific breakthroughs far beyond our current imagination.

Thus, it seems “Chips on String” would not be too far off from becoming the primary form of electronics.

Jason Kim.

Magma Design Automation is hanging in there as one of the big 4 public EDA vendors.  In a recent discussion with Bob Smith, VP of Marketing, who returned to Magma in March 2009 after a several year absence.  The discussion centered on a general update on where Magma is and what they are up to.

Mr. Smith’s marketing position is mostly focused on the digital products, so we did not have a discussion on the cell characterization tools or the analog products.  His understanding was that those areas were doing well based on customer feedback and benchmark data.

On the digital side, the first point that was made is that Magma is very busy on new technology having the tools be used for over 70 tapeouts at the 40nm node and they have a lot of activity at 28nm. In this definition, a tapeout is a design released from engineering to a fab. The tools are also still being used by customers at technologies back to 180nm, and in most application of really big designs.  These large designs (running with Talus Vortex v1.1) are typically 2M-3M instances that are being placed at the top level of the chip.  These large designs are typically flat (i.e. non-hierarchical) at the top level or they are flat “megacells” for use in other designs.

The other common trait of these designs is that they are low power designs which utilize multiple power rail pairs.  These multiple power rails can be automatically connected as separate voltage domains and support most of the low power methodologies including DVFS.  The Talus platform is also the only commercial package that is supporting BOTH UPF and CPF low power design methods.

There were two other points of benefit for the new platform – (1) it runs on a fairly minimum hardware platform – 4CPU, 32GB RAM, multi-threaded Linux (Red Hat / Ubuntu) and (2) the clock tree synthesis is now functional as a Multi-Mode Multi-Corner (MMMC) solution tool that can produce both flat and hierarchical clock trees to the Magma unified data model.  The direction for product improvement is on handling larger designs and additional variation for the MMMC analysis on the same minimum hardware configuration.  The target for all of these analysis is to maintain or improve the QOR for the designs.

On the topic of other products, their physical verification tool – Quartz, is now seeing use with a growing number of customers.  The big change in the product that prompted the increased use is the ability to natively read the SVRF rule file format used by the foundry supplied Calibre decks.  This eliminates the end user from having to translate and re-qualify the runsets for a given technology.

The financial position for Magma has been under discussion and rumor in the industry almost as much as the product direction.  Without going into all of the details, most of which are on the Magma web site with the transcript of the last quarter’s earnings call, Bob indicated they are doing OK.  They have had three consecutive quarter where they were cash positive at levels of single digit $M.  The concern during late summer was their structure for dealing with the bond that Is due in April of 2010.  Magma has successfully re-structured this note with over 50% now being deferred to 2014, and available funds or other payment structures for the balance.  The end result, is the April note is now a non-issue, and the company has an on-going positive cash flow.

PC

At the 2009 International Electron Device Meeting (IEDM) Numonyx presented 4 papers about their advances in phase change memory based on their 45nm 4th generation test chip and process development.  These were in addition to the announcement that the 90nm 1GB PCM part was going to be available as a production product in Q1 of 2010.  This part has a pinout compatible with existing flash parts of the same configuration so it can fit in existing sockets.

The 45nm technology was selected for the 4th generation, continuing the technology node jumping that has been a hallmark of the PCM development since the 2003 JDP with Intel and ST, to get tot he goal of litho parity with DRAM and cell party with flash.  The new LP 45nm devices achieve a cell size of 5.5 feature sq, flash is at levels of 5 feature sq, and DRAM is at 6-8 feature sq.  The new 45nm product is targeted at enterprise class products and results showing reliability at those targets were achieved.  Results in tests based on direct bit addressing showed 1M cycles of write endurance, data retention over 10 yrs.  These are based on a 1.5v socket, where the lower power is achieved through zero (0) effective standby power and active power about the same as DRAM.

Additional papers covered the 3D aspects of PCM.  Papers were presented that had a thin film diode element for the select device in addition to the memory element, in a crosspoint array.  This would allow for veritical stacking of the memories which could reduce the effective cell area up to factors of 4 with a 5 layer stack.  The JDP with Intel has produced a 64MB device with multi-level PCM memories using both thin film (TF) select and memory devices.

The last paper presented the use of PCM in embedded applications. This utilized a standard CMOS select device with a PCM TFT memory element located over the active select device.  The memory core in instantiated as a standard macro block into a P&R flow and has normal keep-out and routing rules.  The major design consideration with the use of PCM in an embedded application, is the thermal properties of the memory element.  PCM memories are thermally programmed, as a result, any design with an embedded PCM memory will have to be after board assembly programed, as the solder reflow process (typically 130o ) will cause the memory to reset.

PC

This week at the International Electron Device Meeting (IEDM), NEC presented their improved 40nm low power CMOS process that has been targeted at RF and mixed signal.  One of the major issues in addressing higher speed data communication for LTE, WiMAX mmwave and other protocols, is implementing analog transistors with high enough bandwidth to make functional amplifiers.  NEC has created a selective copper plug, called a Partially Thickened Local Interconnect (PTL) on the gates of devices.  This PTL interconnect reduces the resistance by 50% in the horizontal direction as well as a vertical resistance reduction.  (See figure 1 for cross sections of low-k process).

Figure 1 - PTL Cross Sections

The PTL interconnect does not impact the design rules of the process and can be implemented as needed.  As there is a increase in contact area, there is an associated increase in capacitance, which is proportionally less than the benefit of the resistance reduction.  As there is a capactiance increase, the PTL interconnect is being segregated to use only on gate electrode connections.  The use of the PTL interconnect allows for Fmax of the devices to be greater than 200GHz which enables data bandwidths up to 60GHz for fuctional RF front ends.

The process enhancement includes the ability to create these larger (non-uniform, non-minimum size) contacts simultaneously with standard contacts and NOT affect the process variability or component reliability.  This is accomplished with a Low O2 etch which slows down the etch rate for the larger openings and also does not impact the either the shot noise or the base thermal noise curves of the device.  The use of the PTL interconnect on the gate, results in a devices with a lower functional noise performance as the reduced resistance lowers the thermal noise of the device.  The experimental results have indicated that none of the device operation features are degraded with the additional of PTL.

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ST Microelectronics followed up discussions on the MEMS marketplace at the MEMS Executive Congress with their major technology partnering announcement with OMRON today.  ST has been a long time leader in MEMS technology and supplier to the CE space.  Their technology agreement with OMRON bring advanced sensor technology and audio/acoustic expertise to the ST Micro manufacturing program to produce high performance MEMS microphones.

Traditionally, cells phone, laptops and other voice capturing CE device use electret condenser microphones (ECM) based on performance and price point. New portable electronic devices and health care electronics are running into EMI, mechanical vibration and temperature sensitivity issues.  The new MEMS microphones will enable both the performance and price point (under $1USD in high volume including control electronics) for these applications.  According to iSupply, the market is growing at 18% per year and should be over 1 billion pieces by 2013.

The MEMS market is currently fed by both IDMs and a large fabless supply chain.  There are major growth areas in this market and the big players are leading the way.  Benedetto Vigna, Group Vice President and General Manager of MEMS and Healthcare Division, STMicroelectronics said “This market can explode only with big and long-term committed suppliers, operating their own leading-edge MEMS fabs. Working together with our Japanese friends, we’ll drive the microphone market growth as we have done in motion sensors.”

The technology partnership has been in progress and will product samples of a single package with the OMRON MEMS sensor with the ST electronics by the end of 2009.  “OMRON is ready to support ST in shortening product development cycles and time-to-volume for high-performance, cost-competitive silicon acoustic devices, accelerating the growth of the MEMS market and the development of new application areas such as voice-enabled gaming, automotive voice systems, acoustic sensors for industry and security applications, and medical telemetry,” said Yoshio Sekiguchi, General Manager of Micro Devices Division, Micro Devices Business Development H.Q., OMRON Corporation.

The MEMS and health care products markets are two of the high growth areas for the near future.  This announcement is indicative of the repositioning and partnering that will be taking place in the supply chain to best take advantage of the worldwide business climate.

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