Pallab’s Place

The service business at Cadence has been steadily operating at over a $100M/yr run rate.  Their services group has been in place performing tactical design for clients (chips and IP), tactical CAD support file and technology file/application program file creation and flow/methodology creation.   This projects and billings for the group have been organized for milestone based funding releases.  The current economy has forced a changed in this model as a rolling cash flow and time based releases have become a big issue for most clients and for the service group’s revenue recognition.  This change has driven the Cadence services group to add a SaaS (Software as a Service) model to their offering.  The offering and the technology has been developed and deployed on a selective basis for the past 8 years and currently supports a less than 100 clients.

Cadence’s solutions offerings are split into five areas: Systems, Enterprise Verification, Low Power, Mixed Signal and Advanced Nodes.  Their SaaS offering is focused on the tactical services offerings that can use defined and stable manufacturing flows and tools - these are Enterprise Verification, Low Power and Mixed Signal.    These three areas are being addressed with a service offering that includes an IT configuration (both client and supplier sides), training for both products and design applications, an engineering/task based outsourcing and the design environment/flow.    This offering is being brought out as a business unit based on recent survey results showing on a typical design project, 17% of the budget was EDA Tool cost, and 23% was time and resources to develop and implement the production environment and flow PER DESIGN.

The model that is being used is that of a traditional ISV scenario.  The service offering is presenting not a pure play SaaS model where the software is just placed in a cloud to achieve higher availability, rather is is an integrated hardware, software and service offering following the model and techniques of ISV leader Oracle.  The Cadence solution uses for following mapping of the Oracle SaaS stack model:

* Access and management : Environment management interface and Remote user desktop

* User interface : End-to-end use model(s) [flows, methodologies, best practices, etc]

* Integrated Software :  Cadence products and solutions

* Database :  Design database storage

* IT Infrastructure : Secure Networking and High performance compute resources

In the new solution the Customer Site only needs to host the design team, a small IT staff and the Cadence remote desktop connected through a VPN.  The Cadence side of the VPN is a hub that consists of Managed design and IT services, compute resources, the design database and packaged design environment with software access.  These hubs are located in 11 location world wide to insure data transfer and access availablity.  These 11 sites are also high availability compute centers with downtimes ranging from 28hrs/year (99.671% avail) to 0.4hrs/year (99.995% avail).

The SaaS programs are project solution based, not tool availability solution based.  This is not simply purchase access to X number of simulation runs or a bag of tokens that can be used on more than one tool in a product family.  The basis is the leveraging of a standardized design environment (naming conventions, scripting, tool sequence, netlist formats, BIST procedure, etc) for a given foundry/process selection.  The use of these standardized environments can lead to schedule improvements of start of design for a full design team in 1 week vs prior project 3 months.  This improvement was obtained by a new medical device manufacturer.

The SaaS model is an service level agreement, so levels of support, mutual resource allocation, length of data retention, data recovery and backup and IP access/compatibility with the flow are all areas of contract negotiation for the projects.  This offering is available now from Cadence.

PC

The Zigbee Alliance has recently approved Freescale as the first “Golden Unit Status” provider of their RF4CE protocol products.  The RF4CE standard is another communication protocol for the 802.15.4 MAC/PHY 2.4GHz radio that supports Zigbee and Zigbee Pro.  The same base radio can be used and the multiple protocols for 2 way communication are possible to exist simultaneously.  In order to have communication between these protocols, a proxy is needed.

The RF4CE standard is targeted for the Consumer Electronics applications as an RF alternative to IR, Bluetooth and WiFi solutions in TVs, Set-top box , media control, home computer and other function control consumer electronics applications.  The system is frequency agile so it will not conflict with neighboring systems and can support two stacks at one time.  For Smart Energy Applications, an IP stack is being developed.

The TV industry had been quick to adopt this technology, which is in production and has been shipping to OEMs for some time.  This quick adoption was brought on by providing a solution to the IR remote interference problems that are generated by LCD TVs.  The technology also has a very low power footprint.  Traditional RF remote solutions utilize 2 AA batteries with a 1 year functional life.  The RF4CE solution uses 2 AAA batteries with a 2 year functional life (four times lower than an IR remote) while still providing 400M line-on-site communication.  This communication range is significantly larger than Bluetooth and IR technology.

At this time the Freescale solutions are being provided to OEMs of TVs, Set-top Boxes, Blu-Ray devices and are being designed into a new generation of smart white goods.  These current products are supplemented by a platform solution that includes and ARM32 bit core, the RF and necessary passives to make the system functional.  This is being made available as both a demonstration and development platform.

Freescale estimates that in 2009, there will be four million shipments of 802.15.4 based RF transceivers for consumer electronics.  By 2012, They expects there to be more than 160 million products shipped per year using the ZigBee RF4CE technology.

PC

The semiconductor industry and other IP oriented businesses have to transmit confidential documents to both members of the company when they are in remote locations and to third parties (customers, partners and vendors).   This correspondence with confidential value includes price quotes, RFP responses, roadmaps, specifications, competitive analysis, product design options, and business plans, The primary method is through the marking of the document as confidential on the document and then distributing it normally.  This normal distribution includes email attachments of the actual document in standard business format (ppt, doc, xls, pdf, etc).

The difficulty with this approach, especially if you are dealing with early release information or raw information is, control of the document after distribution.  Confidela has developed a web based application (in its current form free to use at http://www.confidela.com ) called Watchdox.  The product is targeted for several applications including the secure handling of presentations, data and quotes/documents relating to IP and products in the semiconductor industry.  The key aspects of the product are the encryption of the document, the ability to validate the recipient of the documents and restrict their ability to forward, print, copy or view the document.  The view restrictions are currently in the form of expiration time for document access and a second level of security which visually masks the document on the screen with the exception of a “spotlight” window magnifier which revels portions of the screen selectively with the cursor so he content can be read but not screen or photo captured.  The documents under this system can be protected with a watermark in case the print fucntion is enabled.

Unlike the current method where the physical document resides at the recipients site and necessarily their backup environment, the Watchdox system uses a cloud based encryption and data storage model.  In this method, all of the documents being sent in a secure manner reside at a safe third party location with only the notification email directly being sent and residing on the recipient platform. The product works as a thin client app on most hardware if Outlook integration is desired, otherwise there is no installation on the either the sending or receiving platform..  The product is very well adopted to the various use models of the corporate community as it is a single step authentication over a browser.

The tracking history of the document and the reader is currently supported, and future releases will support a full administrator console for complete and complex policy monitoring.  The initial web release supports 16 file type under their encryption model.  They have a roadmap to add associated encryption and tracking of attached data files that are in archive or compressed format, but they are NOT planning to embed encryption inside of the compression step for the attached files.  The WatchDox system is available for use right now at www.watchdox.com.

PC

Two of the founding members of Nassda Corporation have started a new EDA firm focused on post layout RC extraction.  The new firm Silicon FrontLine was formed in 2005 and formally funded in 2007.  The company is introducing two products F3D which is a Field Solver based RC extraction tool and R3D which is an On-Resistance modeling tool for power devices.

The F3D tool is targeted at “guaranteed accuracy” under the assumptions that if the correct process technology is input, then the results coming from a full field solver should be the “correct” answer.    The core of the Silicon FrontLine technology is on the rapid solution of the field solver and the identification of the conditions and situations to which the solver is applied.  The solver is multi-processor, multi-core and distributed aware, so high throughput is possible with most compute server environments.

As a result, the product can be integrated into standard physical verifications flows from Mentor, Synopsys, and Cadence.  The flows can use either flat or hierarchical design methods, and verification flows, the results come out as a flat netlist.  The F3D tool produces RC netlists and the R3D product produces detailed resistive structures for power devices and large drive transistors.  The integration with the standard flows provides the option of either letting the standard PV tool identify and extract the devices, and leave the interconnect for the F3D and R3D tools or re-code the device recognition for the SiliconFrontline tools and have it identify both the devices and the interconnect.

The current release of the toolset is available for the Linux platform and supports its own technology file format, standard GDSII data input, and outputs SPICE.    The mesh structure of the tool allows it to target advanced applications such as image sensors, data converters, non-uniform current flow, and complex post layout mfg effects such as CMP and metal fill.

For advanced process nodes (e.g. 40nm) the tool has been correlated with both measured and simulated results, and shows single digit percentages of discrepancy in a large number of cases.
Information on the products can be found at www.siliconfrontline.com

PC

Synopsys has finally released the long awaited next generation physical verification product to Hercules to address ultra sub-wavelength (45nm and below) process technologies.  The new product is called ICValidator and works as an add-on/integrated product to the ICCompiler product.  There are three (3) areas of major overhaul and change over prior products: (1) The product is natively written to support multi-core, multi-processor and distributed environments, (2) there is a new programming and control language (PXL) and (3) the complete re-architecting of the product to support both polygon AND edge based verification and logical operations and objects.  The change to support both polygon and edge based verification now allows for high throughput of gridless processing of both design data and blockage data.

The updating of the code base from a single core, single process task to a multi-core engine, has several impacts.  Not only is the design data segmented into multiple machines and processors cores but the runset is also distributed.  The new parser can split the runset to work on separate processors although, the algorithm for doing this was not discussed, the Synopsys staff indicated that the multi-generational historic issues of hierarchical data and flat data in combination with common sizing and spacing rules no longer is a problem for the runset splitter which supposedly now results in near linear scalability with processor count.

The ICValidator product is a supplemental licence to existing Hercules licenses for most users who are migrating to the new processes.  The staffing requirement is that the same personnel would be able to support both programming languages as the new PXL language is easier to use, smaller and more compatible with object oriented construction as the other Synopsys programing languages are.  There are training and transition programs being put in place at Synopsys and new runsets should be available from the foundries.

The ICValidator product is designed for use in an interactive flow that is closly tied with the ICCompiler product.  The concept is to create a closed loop “single pass” between the design creation and actual clean design closure.  The loop includes timing aware routing, timing aware ripup-and re-route for drc repair (i.e. fixing PV errors automatically including multi layer edits), full custom editing modifications both manual and automated, PV and DFM as required.  The new flow is targeting the loop happening at the design creation stage of each design module as it is initially created, this making a “correct by construction’ block, and having just a final assembly level “sanity check”, rather than the traditional, complete a full design and then do full hierarchical PV and have to perform, correct and re-validate the entire design due to corrections.  The correction methodology is such that for sub 45nm processes, it is preferred to leave out complex routing constraints such as corner rules from the router, and then have the PV tool flag and repair the error in a smaller area.

The idea to integrate the ICValidator product with ICC as a combined flow tool is interesting.  Either they have new EDA marketing people who do no know past campaigns, the memories are short at Synopsys, they believe the memory of their customers is short, or their optimism is higher for the re-use of the tag line “single pass” from the old Avant! Aquarius and Vericheck flow. The marketing concept is good of a one step solution, however the execution of the old “single pass flow” typically did not come out shorter than mid 2 digits worth of spins per blocks (as compared to 3 digits of spins per blocks with other tool flows) for real chips besides the powerpoint benchmark chip.  This flow with the ICC integration, PV& DFM and autofix seems targeted towards the same fate.

Synopsys is known for bringing out strong technology products that actually perform well in real applications, for real engineers, and making sure they are stable when they are released.  It looks like this is just such a product and in reality will be strongly embraced by both the foundry and the design communities.

It would be beneficial to these communities if the marketing information associated with the products were directed toward real features of the product and how they apply to actual design data (about 20% of the current pitch info) instead hype that is re-tread from the Avant! flow slicks cira 1990’s.

PC

The past few years have seen the video broadcast industry dealing with a creeping need for bandwidth and throughput.  This was also met with a trend toward the use of IP blocks in SOCs to address some of the many different avenues of the broadcast marketplace.  The key pieces going into these SOCs the past couple of years has been the SDI interface blocks and the different types of video protocol converters (JPG2000, MPEG4, etc).  The majority of these designs were being implemented in FPGAs.  However, as the transition to digital broadcast becomes immanent, more studios and stations have opted for more traditional high performance specific task hardware that is optimized for the specific broadcast functions.

Gennum has addressed this need for high performance standard products with a group a 10 new 10Gb/s SDI chips that were introduced in April 2009 and demonstrated at NAB.   Gennum initially was a small mixed signal semicoductor company focusing on video, data converters, hearing aids, and custom mixed signal.  They have now rel-aligned and re-targeted on the markets on Video Broadcast, Data Communication, A/V Connectivity and IP Core Licensing.  The current corporation is operating at a 2008 revenue of ~$127M USD and 76% gross margins.

Using these resources, their R&D was able to deliver the following products which may be available as IP cores in the future. One is a3GB/s receiver with equalizer that can drive 160 meters of coax cable.a 3GB/s video optical receiver module that is “error free” over a 60km link, capture solutions using new PCIe bridge and PCIe extender products, and finally a new class of power efficient equalizers, reclockers, and cable drivers.  These products are all either sampling or available in 2009.

PC

Dr. Chi-Ping Hsu is the Sr. VP of R&D of the Implementation Products Group at Cadence.  Dr. Hsu come to this position at Cadence from key technology leadership positions at Get2Chip and Avanti.  Under the current version of organization, this group is responsible for several product areas - CIC: Virtuoso and other custom physical design tools, CSV: Simulators and DFM/Litho products, ICD: Place & Route / Signal Integrity / Timing, and SPB: PCB / SIP and Packaging.  The group is also responsible for several industry initiatives - the long standing Open Access (OA) database initiative, the Power Forward Initiative and the new Mixed Signal Initiative.

The reorganization is centered around the strength of the new anchor products.  The feature sets in IC 6.1.3 that are part of the open access versions of Virtuosos and EDI (Encounter Digital).   These tools while incompatible with prior design data from version 5.1.41, has been receiving strong responses from customers who have chosen to recreate designs from the ground up in the new tools and simulate them with the new simulator.

The new environment also hosts a new line of multi-threaded and multi-core aware simulators that are a departure from their traditional single core products.  These multi-core products provided increased throughput of 12-20x over the single threaded products.

The current flagship of the new product is the low power solutions under the common power format.  The low power solutions both in products and services are an integral portion of the revised Cadence design platform.  It is addressing the advanced process marketplace in the low power SOC application space that does not rely on legacy data, so entry into the new tools and new simulators is not an issue.  The use of the new tools results in the use of new flows and new services and support infrastructure.  On this basis, Cadence sees a strong business case for those that choose to adopt the IC6.1.3 platform or the Low Power Solution/CPF format.

pc

Todays PC systems are protected by 4 basic hardware passwords a user and an admin password for accessing the motherboard and a user and an admin password for accessing the harddisk.  In most enterprise environments, these passwords are not used, due to the difficulty in administrating them.  As a result, most data is not is not fully secure in design and compute environment.

Lenovo started 4 years ago to address this issue by implementing a bios level solution to the problem.  They have just released their hardware password manager that introduced an IP telecom stack into their BIOS. This is a custom modification of the standard Phoenix BIOS that has been provided with their Thinkpad products.   Unlike the Intel Vpro solution, this is not a chipset or cpu specific solution, it will eventually support all of their platforms.

Providing these functions to IT administrators so they can  remotely manage employee hard drive passwords, including drives that are self-encrypting, the new tool can help companies reduce the time and expense associated with recovering and resetting employee passwords.  The BIOS level hardware password manager allows a standard wired network connection to be used to verify, change and support the motherboard and harddisk passwords.

This methodology supports all brands of FDE (Full Disk Encryption) self encrypting drives. The password control works for both local drives and any network attached drives that released at the time the passwords are cleared.  This password control also works with fingerprint scanner authentication.  The password control for the motherboard controls the powerup control and provides a “ConstantSecure” Remote Disable function which allows a user to remotely disable a machine if lost or stolen the next time it is connected to the internet or attempted to be powered up.

Lenovo Hardware Password Manager will be available worldwide starting in early May.   A video link of the product at work can be found at YouTube at:  Lenovo Hardware Password Manager

pc

A new industry initiative (www.ebeam.org) has been brought to the design marketplace focusing on a cost effective solution to the low/mid volume and prototype requirements on cutting edge deep sub-wavelength processes (90nm and below).  The managing sponser company D2S, Inc has brought together a strong initial partner/member base, a strong leadership group, and a very directly focused goal for the group.  Aki Fujimura (EDA veteran most recently from C-Level positions at Cadence and Simplex Solutions) has organized a group with the simple focus of creating a design and supply chain for prototype manufacturing without masks that starts with optimized design data and software, and goes through a modified data fracture environment to direct write of wafer via e-beam on new optimized fabrication equipment.

Based on the directed focus of the initiative, the dramatically increased cost of masking and fabrication of sub 90nm processes, and the current world economic situation, all aspects of the design flow have chosen to participate from the initial stages.  These partners can all be found at http://www.ebeam.org/members.  The group has already started a 65nm prototype as proof of concept on the flow back in Oct 2008, and the run is a collaborative effort of the partners D2S, eSilicon and Fujitsu.

A change in this design solution, is rather than being an after-the-fact DFM correction flow, the design starts with IP that is optimized for the fracture routines and the design patterning optimization of the direct write e-beam equipment.  As such, the level of optimization sought and can potentially be provided is well beyond that of any single point in the flow optimization solution.  Several differentiating aspects from other “DFM like” programs is the inclusion of members such as Tela Innovations and Altos Design, which are in place to validate the usability of the design IP for both the customers and in real tool applications.

To help bring structure and organization to the initiative, they have enlisted the services of another multi-disciplinary veteran, Jan Willis, as the initiative facilitator.  Jan is well known form her work at Cadence on the industrial relations/partnering side and as facilitator for the the X-Initiative.

The program is targeting an anticipated design throughput by the end of 2009, of 1 direct write wafer/hour using the proper design libraries, VSB (variable shaped beam) fracture and CP (character projection) fracture on the newly design equipment and flow.  This is definitely a program to keep track of, as the solution can mean high 6 figures/low 7 figures of cost savings per design using a direct write methodology over a masking and MPW prototype flow.

PC

Opening Address by MUSIC Chairman Dr. Uming Ko, senior fellow and director of the Worldwide Chip Technology Center from Texas Instruments. 150 attendees were registered and the opening address had one third of them. Dr. Ko opened MUSIC on a positive note looking at the new problems we face in the industry including the economical downturn as challenges. Point being the feature sizes keeps reducing further and all the devises that we use must have portability, ability and capability. The challenge today is the batteries ability to power the devices.

I drifted between the various sessions by Magma and customers: TI, nVIDIA, IDT… The excitement at the user conference were lingering in the sessions, initially covering Titan’s ability and Talus’ speed improvements in the Analog Design and Circuit Simulation covering highly intensive migration across Analog and Digital domains, through Magma’s new approach to mixed signal portability that is being developed as I write.

I ran into Magma Chairman and CEO Rajeev Madhavan in the hallway who was bubbling of excitement that one usually sees when companies back in the late nineties were about to be acquired. However, his excitement was, at the show, about being able to migrate mixed signal designs both logic and analog, from process node to process node once the designs were in the Magma systems, the announcement will be announced at DAC in San Francisco in July. Rajeev also mentioned how they have been able to reduce Talus’ runtime by 3X and expects to see further reductions by September of another 2X.

Rajeev’s excitement carried into the Keynote where all the 150 attendees patiently waited. Rajeev started with a quick look at the economy which along with many other things has forced Magma to do things differently and go “back to basics” (haven’t we all been forced to that lately), and focus on the core values. Magma can’t succeed alone on “me too” solutions unless one can show a 10x speed improvement, and thus Magma’s new breakthrough with analog migration. So what’s next: Last year Magma’s focus was productivity for SOC designs and they claim the ability to handle up towards 100M cells in the next 6 months by parallel distribution of the various blocks. In addition, the support burden has been reduced along the runtimes. However, the excitement that was left hanging after the keynote, was the announcement of Titan’s ability to, once design has been captured, with some work in capturing it initially, move the designs from process node to process node, enabling one environment for analog and digital designs = TITAN.

We have been facing the same “me too” issues at Nangate until we enabled application specific library development capabilities. DIFFERENTIATION IS KEY IN THIS ECONOMY!

Jens C. Andersen, Special Topic Editor for Extension Media, and VP of Worldwide sales and Managing Director of US Operations for Nangate Inc. Nangate develops tools to create standard cell libraries, and optimization tools and services enabling application specific libraries resulting in optimized speed, area and power. jca@nangate.com