Pallab’s Place

The IEEE’s Electron Device conference has traditionally focused on advancements in process technology, new devices and the modeling and understanding of how these devices and the process chemistry/physics works. The conference has been and continues to be the main stage for the announcement of new and novel devices, new process migrations, and new analysis techniques to being able to monitor these devices and prepare them for volume manufacturing. Registration and attendance was high in the context of the current economy and industry environment.

The conference has not been a strong hold of circuit design and system application information, except for memory technologies, as that has been covered by other IEEE societies and events. This year’s conference has shifted this trend and full acknowledged the tight coupling of generalized design tradeoffs and process technology for DSM and Nanoscale processes. The conference featured several keynotes on this topic as well as several full sessions. The sessions included: Nanotechnologies for Medicine and Biology, Biosensors and 3D Hetero Integration, and Issues at the Confluence of Technology and Design.

The Medicine and Bio sessions presented information that was very representative of the direction and challenges in this area. With an audience comprised of both design engineers and process technologists, aspects of bringing bio products to production ranged from:
- system segmentation (internal, and external partitioning of hardware, software & UI control)
- system packaging and interconnect technology for multi-chip systems - flexible vs traditionally rigid structures
- Power and temperature constraints - most electronics utilize external power that is replaceable and power issues are bsed on extending battery life. In the Bio interface designs, operating temperature changes in excess of 0.1C are a problem for implantable devices as well as the requirement for passive power coupling to avoid repeated invasive procedures for battery replacement.
- drug delivery options that take advantage of MEMS and Nanowire technologies. These papers presented how to use standard, proven, electronic MEMS processing or Nanowire growth on spheres to create solution options for directed point of treatment. The MEMS product was a series of electronicly controlled reservoir chambers that could programmed for release on a fixed long term program basis. The other paper described standard nanowire creation to make absorption optimized drug delivery spheres.

The Biosensor papers were very circuit and design oriented rather than process technology oriented. There was nice background to the attending audience for the DNA sensitive FETs and the modeling behavior that goes with the design. This session also covered nanowire sensors and 3D assembly techniques including TSVs (Thru Silicon Vias). These assembly techniques and sensor materials are new applications of process technology that was nominally targeted towards multi-chip high density memories.

One of the larger sessions at the conference consisted of ONLY invited papers and focused on Issues at the Confluence of Technology and Design. The first talk , by Professor T. Sakurai from the University of Tokyo focused on technology behind low power design methods, those that are circuit derived and those that are process derived and their impact on potential yield and manufacturability. The premise being only small portions of the design are performance critical while all devices present in the design are power critical.. The second talk, by Professor P. Gupta from UCLA will discuss the use of devices with tunable parameters that can be implemented late in design cycle. The key is to allow for tunability, not redesign, that will help meet production requirements without the need for a full re-characterization cycle. The techniques reviewed included some that are already part of OPC and post processing capability but not part of any standardized flows. The third talk, by Professor A. Strojwas from Carnegie-Mellon University and PDF Solutions, was somewhat contrary to the the second paper, in that it adovcated reduced design rules and as the method for tradeoffs between yield, variability, and robust design. The fourth talk, by Professor A. Asenov from the University of Glasgow, addressed the exponentially increasing area of analysis of variability and its impact on design using statistical simulation techniques to model variability and reliability in highly scaled devices. The last three talks addressed specific application areas and technologies. These talks were by Professor D. Sylvester from the University of Michigan on the design of robust low-power circuits; by Professor K. Makinwa from TU Delft on CMOS temperature sensors; and by Professor M. Horowitz, from Stanford University will focus on the requirements for future devices intended as CMOS replacements.

pc

Samsung recently held thier annual technology forum and analysts event.  The discussions covered the topics of Digitial TV, LCD panels, Mobile Communication systems divisions as well as the Memory and System LSI component divisions.

The memory division separated their discussion into the areas of DRAM and Flash.  Due to the worldwide economic conditions, both of these divisions showed weaker performance than expected, however they are both targeted to finish the year in a stronger position than thier competitors in these marketplaces.

Currently, Samsung DRAM technology is using a 56nm process line rampup., Due to severe price erosion in the marketplace and a drop in market demand, has an end retail price very close to the manufacturing costs.  In response to this situation, Samsung is planning to dial back the schedule on the production ramp for DRAM.  The DRAM process migration is moving to the 4xnm and 3xnm modes to address the DDR3 products.

Thier NAND market situation is very similar to that of DRAM.  They currently have a rampup in progress on the 42nm node and the goal is to produce products in sync with the industry embracing   SSD technology to utilize the NAND Flash product.  Thei SSD (Solid State Device) market is a driver forthe 2009-2011 market.  In order to address current market positions, Samsung will be cutting back some of thier 8″ NAND capacity.

In addition to the standard memory products, they have been enhancing thier multi-chip module capability.  Thier newest designs use TSV (Thru Silicon Vias) have been tested using a 32 chip high stack.  Most of their MCP stacked products are 9 chips high, 8 memories and a control interface.  These will be used in the DTV, Mobile handset and SSD market applications.

The NAND products for SSD applications are targeting the 42nm process for ‘08 and shifting to 3xnm nodes for ‘09.  This will address the ‘08 products using the SATA2 (3GB datarate) spec and the ‘09 products using the SATA3 (6GB datarate) spec.  The NAND products are moving from a CE based application to include an embedded application base.

To simplify application in the embedded space, Samsung has introduced the OneNAND product.  This is a multi-core product that contains traditional NAND high capacity cores a;song with high speed SRAMs and a NOR logic interface with ECC logic.  Although the OneNAND product was introduced in 2003, they are now in volume production on the 51nm node at 1, 2 and 4Gb capacity and at 42nm node for the 8 Gb product.  These products can currently be found in thier higher end mobile phone products.

The architecture and and business model for the OneNAND product line has been adapted for the introduction of the OneDRAM product line.  The conventional solution for mobile video requires two (2) RAMS.  The OneDRAM product allows a single memory to meet the requirements of botht he baseband and application CPUs which can result in a significant performance increase over standard 2 memory configurations.

The LSI division has migrated from internal use function specific component solutions to full SOC platform solutions.  These include leveraging their low power process technology, CPUs, advanced IP and memory solutions with assembly into Mobile SOC soltions and system level optimization including UI and software development.  Some of the key points of this offering are the jointly developed Samsung/IBM 32nm HKMG (High K , Metal Gate) process technology which is offering a ver low power high performance option and the POP (package on package) solution incorporating OneDRAM technology.  The POP solution allows for the stacking of an application processor and a NAND/DRAM MCP in a single 16mm form factor package.  This reduces I/O through the use of high speed serial interface vs traditional parallel interfaces, increased performance, reduces EMI and meets the form factor of the end application such as mobile communication or image capture products.

One of the last areas of discussions was the digital imaging and mobile camera productsproducts.  Following prior attemts by Samsung and other companies, they have reduced the pixel size to target higher resolutions and are attempting to address the depth of focus and brightness issues using backside illumination.  This may result in an increased sensitivity of the design, but has historically resulted in a yield and quality reduction that offset the benefit of the sensitivity increase.  It remains to be seen how thie attempt works towards developing auto-focus, extended depth of field camera phone products greated than 5MP in resolution.

PC

Adobe Design Systems held thier annual MAX event in San Francisco in Nov.  The event was split fairly evenly on still image/document creation and moving image (video and MID content) creation.  One of the high points was the use of multi-processing and hardware acceleration on the current releases of the design software.

The Adobe CS3 product has been optimized for the the multi-core Intel processor architectures at the 65nm & 45nm nodes (Penryn microarchitecture).  The product is now multi-threaded and multi-core aware for the After Effects module and most of the rendering tools.  The tool set was created using the Intel developer tools including Intel Vtune Performance Analyzer, Intel Thread Profiler, Intel Integrated Performance Primitives and the Intel C++ Compiler.  These tools allowed Adobe to address and optimize use of the 47 commands from the Streaming SIMD Extensions (SSE4).  Under the Windows XP 64 bit OS, the results of these optimization methods and the advanced processor support, allows performance such as a real time cross dissolve of two (2) HD (720p) MPEG video streams using Adobe Premier.

The CS4 products and many associated add-ons (e.g. GridIron Software’s Nucleo Pro 2) are continuing this multi-core optimization.  This multi-core & multi-threaded support represents pretty much a wholesale rewrite of the main code blocks of the program.  The performance enhancements and new capabilities possible with the product appear to have produced a payoff that justifies the risk of the code re-write.  This trend is continuing with the add-on products to the CS3 and CS4 family.

One of the other acceleration options that was presented was the Nvidia Quadro CX grsphics accellerator card for CS4.  The card utilizes DDR3 high speed graphics memory, a CUDA parallel computing processor, and dual display port/DVI/and analog DAC outputs.  The graphics processor has hardware optimized shader capabilities as well as H.264 rendering technology.  The card is compatible with Win XP, Vista, Linux, Solaris and utilizes a PCI express interface.

Although the CS3 and CS4 packages run on standard (non-optimzed) hardware, the trend is to special multi-media editing and post production machines with high performance features.  These features are designed to handle the large data sizes and high thoughput required to process HD video at full 24 FPS or higher frame rates.

Diane Chatterjee for Pallab Chatterjee

On Nov 6, the SPIE held an interdisciplinary event on innovation that covered the historic, current and future (projected) directions in innovation as it relates to technology. The event was organized by SPIE in association with UC Berkeley and PARC. The program was a one day event that had morning sessions on general innovation and then afternoon breakout sessions on LEDs/OLEDs, Solar, and Biophotonics. The conference was well attended with many diverse personnel from technology, academia and finance.

The lead off question for the event was, Why an Innovation Summit? The consensus from the organizers was that we are currently in a down market, there is no coordinated government support for innovation, there is a large slow down in IPOs, there is currently a poor innovation infrastructure and most emerging markets have a lack of understanding of science and technology’s role in innovation. This lead to the following preface to the keynote speakers: For innovation to be a successful, is it the invention, the business model or both?

There were three keynote speakers - Henry Chesbrough from Berkeley, Robert Byer from Stanford, and author Dr. John Kao. Mr. Chesbrough’s keynotes focused on the shift from the current closed innovation system to an open system. This closed system is the idea of multiple research topics being reviewed and the development being selected as what best supports current and historical business models. The open systems has multiple research topics being reviewed and results in both development being selected for the existing revenue stream as well as development supporting adjacent areas through technology licencing and royalties, creation of spinoffs and valuing IP in both a fully realized and staged mode. The reasons behind this shift included the increasing mobilization of resources and the enormous increase in venture capital. The conclusion was these innovation models were built jointly with business models that creates value for the customers and allows the owner of the model and innovation to profit from the creation.

Robert Byers presented a historical perspective on the silicon valley? model and the close relationship between universities and corporate development. This included the historical interactions between Stanford University and Hewlett Packard Corp as well as the creation of PARC and SRI. The importance of the university knowledge base for basic research and education was detailed as a key for enabling commercial innovation.

John Kao presented some of the concepts from his book Innovation Nation? These concepts included the global basis of innovation, and the what, why and how of innovation. The what was described as creativity for a purpose that applies a value. The why is based on the 3 pieces of innovation - talent, capital and ideas. The how is compsoed of two concepts - (a) having a defined vision that includes a sense of urgency to address it and is measurable and (b) there is a responsible steward for the vision.

The afternoon sessions were high level strategic direction discussions about new technologies being created in the areas of solar, lighting and biophotonics. These were introductions to topics of short term and long term development and the divers for these innovations.

As a kick-off event in a marketplace where even established events are having trouble with attendance and quality of content, this was a very strong event and if the organizers continue to attract the same high quality of presenters, then the event will continue to be well received and very beneficial to the technology and optics community.

pc

Mentor kicked off their 2008 User Group event in Santa Clara this week, with a very good morning attendance for the day after the election and a huge traffic accident messing up traffic for miles in most directions headed towards the event.

The morning had two keynote speakers, Design-to-Silicon VP Joe Sawicki from Mentor and Chad Hawkinson VP of Vertical Market Strategy from PTC discussing a joint program and direction with Mentor. Joe’s Design-to-Silicon group covers the new combo of Olympic SOC, the Calibre franchise and the Test Kompress products. As a different spin on the technology pitch, the discussion was nicely high level and was an overview of some of the design/build information from the SOC implementation perspective and how tools address the whole life cycle of the product creation through production release.

The presentation was thankfully short on the standard DFM SEM photos, the obligatory random defect? photo that has been shown since the late 70’s and the Litho related contour? plots. The presentation, however, did show a strength for Mentor of understanding the IT impact of the current process technology and their approach to tackling the issues. As the process technologies scale down, the amount of content in the designs (geometries, firmware, gates, layers of interconnect, manufacturing/lithography steps involved) does not scale linearly. As a result, the new designs require several orders of magnitude more data to be processed in an ever shortening product development cycle. Mentor has addressed this with aggressive adoption of multi-core, multi-thread and distributed processing for their tools. The methodology includes true scaling from single CPU (multi-core) environments to full cloud computing environments to best optimize through put for design at the IP to SOC level.

The new optimization message for the 45nm and below era is now targeted at workflow optimization as is seen in data reduction, Multi-Corner Multi-Mode (MCMM) analysis, Multi-core Multi-threaded computer environments and the understanding of both technical drivers and business context as parts of the current design flow. The new workflow includes the Olympus SOC product as the central evaluation engine for the variability and power design / analysis issues, the incorporation of CAA (Critical Area Analysis), LFD (Litho Friendly Design) and CMP (Planarity modeling) into the DFM tools and the addition of Yield learning to t the Test Kompress production test environment. This keynote acted as a lead-in to the Calibre DFM roadmap held later that same day.

The second keynote addressed the larger system aspect of the Mentor product offerings. It was presented by PTC and discussed the combined workflow of the PTC MCAD (Mechanical CAD) & PLM products and the Mentor ECAD (Electrical CAD) tools for PCB and system firmware. The new system environment includes interaction in component & board design, revision control, user software/firmware and industrial design aspects of a product development program. The keynote represents one of several partnerships in development at Mentor on the path of component, software, RCS and PLM space. One of the keys in he integration is verification and validation of the design

Mentor also presented thier Calibre DFM roadmap that afternoon. The discussion focused on the new members of the Calbre family - Calibre YA (Yield Analyzer), Calibre LFD (Litho Friendly Design), Calibre YE (Yield Enhancer with Smart Fill Technology) and Calibre CMPA (CMP Planarization Analyzer).

The YA product is an integration of the prior Mentor CAA product with the tools that were brought in from the Ponte acquistion. The product is incorporated into the RVE debug environment and has support for both library characterization level and the full chip level.

The LFD product incorporates variability analysis and identifies design robustness that helps minimize litho related fallout. One of the major enhancements is the ability to perform this analysis in a time scale that is applicable to use in a normal design cycle. Prior generations of tools from vendors in the EDA space, were not capable of producing this level of quality of results in a cycle time that could actually be used as part of a design flow. These enhancements are partially responsible, in addition ot partnering arrangments, to the approval of the tool in the new TSMC Version 9 reference flow.

The CMPA and YE tools are related to both density and litho aspects of the interconnect fill. The YE product uses a new algorithm for planarization fill called SmartFill. This not only operates in 40-50% of the runtime of prior traditional dummy fill techniques but is 3D aware and supports non-rectangular fill so that performance of the fill is optimized. The CMPA tool incorporates features of the new eqDRC capability to allow for equation based descriptions of the design rules. As these features are depth of field sensitive, the tool targets and minimizes overfilling with dummy metal?.

Future directions include Reduced Design Rules (RDR) Physical Verification (PV) that is grid oriented and context awareness for rules.

As a change from the traditional PV direction at the User Group Meetings, the Calbre and Design to Silicon platform were finally messaging the whole flow of the tools from design entry, physical design, verification and test rather than a series of point tools that the customer has to integrate themselves. The support and service model as well as design interoperability that hte customers have been asking about and that they have been presenting results on for years. It is good to see the direction acknowledged and finally moving Mentor from a point to provider to being a solution provider.

PC

The latest changes at Cadence (Fister’s departure along with his gang of VPs) seems to have surprised many, but to most of the people in the design community it was no big shock.  It is just the current state of volatility in a correcting industry that may not survive the correction.  Unlike the stock market and the big investment firms, the government is not planning to use tax dollars to shore up a small boutique industry.

The sector has been self-victimized by the same sort “creative” accounting practices that plagued the dot.bomb craze and the current energy/real estate debacles along with an overall lack of cohesion for a common purpose.  This has resulted in the EDA sector having difficulty justifying making growth, realistic booking goals, a consistent definition of what industries make up the segment and the admission that the cost of development of electronic products (the end customer marketplace) has resulted in a dwindling number of customers that can afford their products.  Cadence being one of the bigger players in the field and promoting the house of cards, is just having an implosion at the leading edge.

What is interesting about the industry and the current situation at Cadence, Synopsys, Mentor and Magma is that the technology they have is actually quite sound and innovative.  To make a very gross high level generalization - Cadence and Magma are having problems with the financial community due to validation and forecast of booking and long term revenue based on not showing the global reduction in design starts, Synopsys and Mentor are getting beat up in the market because they are projecting conservative verifiable estimates which shows slow/no growth in a declining economy.  Translation - if you push the numbers, they street dumps you, if you play the numbers close, the street crucifies you - either way EDA as a sector has a problem.

The recent management at Cadence seemed to be operating under the assumption that their products were simply shrink-wrappable components that could be sold to anyone with the money to buy them.  They also followed the standard product/stocking distributor/retailer premise that new products are at a premium and you heavily discount to clear old products from inventory.  Unfortunately, EDA is a long life cycle business where the maintenance and service revenue from these older products (i.e. simulation tools, custom design, pcb) account for significant portions of the base revenue stream.  These sort of decisions are being made by multiple companies who still believe that EDA is a valid standalone sector.  The reality is that the EDA biz unit came from the electronics supply chain for a full system product life cycle program, and that breakout of “component design creation” as a parallel sector is reaching maturity and the interaction/integration of the tools, planning and manufacturing has to be re-integrated into the product cycle.

So where are we - you have a couple of big boats in the water, without a destination for where they are headed, one does not even have anyone steering the ship.  You have a couple of big boats staying in the middle of the river, heading slowiy upstream and betting that things are better there, but being careful to not crash the boat.  The rest of the private guys are just blinding following in the wakes of these boats, hoping to be acquired and brought on board, even getting on board with the directionless boats.  It would seem, the best bet is it to stop the drifting, nuke the directionaless boats and send the people out on life rafts to new industries, and redirect the two good boats to the semiconductor component and equipment channels where there is at least a positive TAM still available.

pc

Following the recent announcement from Mentor/IBM Cadence’s Design-to-Manufacturing (D2M) solution now includes Source Mask Optimization.  This computational technology was developed jointly with Tessera Technologies.  Tessera is best known in the high density packaging field, however they had a prior acquisition of Digital Optics a leader in illumination sources for industrial applications.

The technology is targeted as allowing for the identification, selection and modeling of both standard illumination patterns (quad, dipole, etc) as well as custom patterns available with off-axis illumination.  The result should be design optimized illumination that is hierarchically constructed to support a single optimized illumination pattern for the whole reticle area.  Similarly to the Mentor/IBM announcement, there are no production lithography tools currently using programable illuminations sources that can use this technology.  Where the Mentor solution is targeting masking and fabrication partners for the development of the technology, Cadence is moving one step earlier in the life cycle by partnering with a component supplier who may be selected as part of the stepper manufacturer’s equipment.

The technique is not targeted at just 22nm, rather it is a generalized approach that can address all sub-wavelength technologies.  The advancement of the technology should result in a more usable set of “working design rules’ rather than the complex group-by-group decisions on required rules, optional rules and suggested rules currently presented by the wafer fabs.

The solution is part of the Cadence Process and Proximity Compensation (PPC) technolgy offering.  It supports bith single and double patterning solutions, is targeted at high throughput and features enhanced rapid design convergence (single digit iterations).  Cadence/Tessera’s simulation have shown that the use of these techniques results in an improvement in process window yield.

As in the other releases in the SMO arena, it is a watch and see technology to determine if (A) the equipment manufacturers can support/adopt such a technology without impacting throughput and reliability, (B) if the fabs and processes can provide support for this additional level of variability to the deign community and most importantly ( C) if the cost of implementing the technology and its associated simulation/IT infrastructure requirements can justify the return on yield for end semiconductor products.

PC

Mentor just introduced their next module to support parallel processing in the Olympus SOC product line. The newest piece is the timing and design optimization portion. These continue the simultaneous Multi-Corner Multi-Mode (MCMM) processing in the physical design arena. The product enhancement is being presented as a paradigm shift for sub-wavelength SOC design.

The premise is that the serial timing closure (timing analysis, goal identification, design re-optimization and then multiple iterations) gets excessively long in 65nm and below processes due to the large variety of corners, modes and design optimization techniques available. The Olympus engine inherently addresses the problem of the MCMM space by creating solution scenarios for the engine to solve. These are a space consisting of simulation states like Power1-Corner1-Control_state1, Power1-Corner2-Control_state1, Power2-Corner1-Control_state2, etc. The new enhancement is for making the timing closeure portion a SMP (Single Memory Parallelization) application for multi-core, multi-thread processors. This allows these multiple simulation states to be solved simultaneously with adjacent cores. As there is already a set-up engine for these tasks in Olympus-SOC, the resulting overhead is just on job launch and results gathering. This allows the performance to be at 7X for an 8 core (dual quad-core processors) machine.

Mentor has taken this a bit further than just timing closure, to includes design closure. The optimization loop includes validation and auto-selection of options such as gate sizing, buffer insertion, path duplication, and logic re-synthesis in order to achieve the timing specification required. As the environment is a physically aware system, SI, EM, IR Drop, and OPC/RET issues are also part of the constraint space for design closure. They use these optimization techniques in addition to the MCMM environment, to identify a solution that meets the timing requirement or indicates that constraints cannot be met.

The automated selection of solutions for the traditional timing closure, including SI, EM, etc, has a known history of acceptance within the design community. The extension to the MCMM decision space may also be accepted in the design community, provided there is traceability to the decision path that was used to find the solution. In these two cases, the decision on meets the criteria or not is a fairly binary yes/no decision.

The paradigm shift that is being presented is not really the adoption of parallel processing to the timing closure task, nor is it the further applicability of the physical awareness to parallel processing. It is primarily the automated selection of design closure alternatives in context of the physical views. As these design optimization solutions have both structural and functional characteristics, the selection of the solution method has traditionally been steered by the designer based on the review of available solutions that are presented. For a large number of the cases, the involvement of the designer to select the tradeoffs in the structural design is not required, as there are usually one leading solution to the design space. The main question as a result of the product release, is if the design community will embrace the automated selection of solutions for the entire design space, and how much manual intervention is supported and easily allowed. If the product is architected correctly, as Mentor is claiming and is being proclaimed in the customer testimonials, then the market will see a big winner and a paradigm shift, otherwise, it is just another one.

PC

Progress on the realization of 22nm wafer fabrication has moved a step closer with the new joint development program between IBM, Mentor Graphics and Toppan Photomask. Coordinated out of the IBM East Fishkill facility (Hudson Valley area of NY) advanced development of a new approach for optical resolution of the critical masking operations for the 22nm node is progressing. The direction be targeted is bringing advanced computing skills to the semiconductor manufacturing ecosystem, not just the design phase utilizing DFM and traditional mask preparation tools.

The IBM facility is a current 140,000 sq. ft, approx 4000 wafer/week 300mm facility with an in progress of being configured 72,000 sq. ft annex. The main fab floor is for 130nm, 90nm, and 65nm production at this time. The annex is in phase 1 at this time and is supporting a mix of 65nm/45nm production and 45nm/32nm process development in approx 40,000 sq. ft. Phase 2 will be the balance of 32,000 sq ft and be targeted for 32nm manufacturing and 22nm development. Process and lithography development down to the 15nm node is being done at their partner facility the College of Nanoscale Science and Engineering at the University of Albany.

The new method is based on expanding some technical and business concepts: (1) computational lithography (CL) which incorporating a manufacturing tool control called Source Mask Optimization (SMO) with Mentor Graphics and Toppan Photomask; (2) exploring development options and strategies through a TCAD based virtual fab in conjunction with Rensselaer Polytechnic Institute (RPI) and (3) design technology co-optimization that is identifying directly measurable manufacturing rules and techniques as a joint effort between Mentor and IBM.

The CL portion is an extension of the existing DFM flow which has focused on just physical design database adjustments using OPC and other traditional MDP products. Mentor has already demonstrated the expansion of their Calibre products to support distributed. multi-threaded, multi-core and other high capacity compute environments. The advanced development work with IBM will include fundamental research on applications with GPUs, the IBM Cell BE processor, and other engines that may be used in a cloud computing or supercomputer environment. The need for this is to provide rapid turnaround on the complex problem solving for the new imaging simulations. The main ideal of the new CL was to develop a method of providing lithographic solutions for specific areas of the chip being processed fast enough to be usable on the factory floor.

This manufacturing floor solution would be coupled with in development, but yet to be available 22nm masking equipment, that can use a programmable or variable light source. Current masking equipment uses fixed illumination sources for an entire reticle area. The added flexibility of SMO would allow for function specific and portions of the reticle (e.g. memory cores, control logic, high speed paths) to not only be optimized with traditional DFM tools, but also add the new dimension of source style (single point, dipole, quad, etc) in order to allow for imaging the 22nm process. This SMO will reduce the high amount of complexity of the data on the mask, and shift some of the complexity to the masking equipment and the light source. The impact will now be both mask and source simulation data processing. Toppan Photomask is participating in this portion of the program to help incorporate constraints on the reticle preparation, use and defect inspection & repair.

pc

Jabil Circuit has been in the electronics manufacturing and supply chain business since 1966. Historically, they were best known for their subcontract manufacturing of PC Boards and enclosures. In the late 90’s - early 2000’s they added in the full supply chain support for the electronic product development market.

In recent discussions with Jabil, they have refined their model and are expanding in two areas - localized supply chain implementation and semiconductor supply chain. The driving forces for this refinement is minimizing the cost and time associated with the logistics of material movement from component production to test to system assembly. In the medial and instrumentation space, the localized supply chain has focused on supporting and supplying ROHS compliant services and facilities as a migration path for their customers. This approach is being targeted at a global expansion model after strong success in North America, solid migration into the European community and early phase in Asia and the Pacific Rim.

The need for this model is to support the increasing diversity of low & mid volume high product mix applications. These applications need a supply chain that not only includes standard subcontract manufacturing of the boards, component assembly and insertion into enclosure but also includes incomming component screening, in-production test, post-programing test, final test and packaging insertion. At this time they are operating/supporting 14 factories worldwide. On the medical side products include: digital imaging, patient monitoring, record keeping and patient bedside PCs and connected display environments, and in-hospital flatscreen/portable products.

The transition to the semiconductor supply chain was actually a customer driven direction due to the progression of System On a Chip (SOC) design. This shift resulted in a reducction of the manufacturing supply chain for a lot of systems to just a component level product, enclosures, memory and displays. In the semiconductor supply chain, they are providing customized build solutions for equipment manufacturers to be able to replica manufacture their equipment, as designed in R&D, near the point of sale, application and support of the semiconductor wafer fab. The supply chain includes both the wafer fab portion of the process as well as the electrical test, packaging and final test portions. The emergence of the semiconductor target model has given rise it a market split of 50% in North America and 50% in Asia primarily in Penang and Shanghi.

This supply chain model, that has been implemented by Jabil, for expansion of the subcontract manufacturing community is the new model that companies are shifting to in order to address the reduced component count of mobile electronic systems and offset the high cost of transportation for people and materials.

pc