Carlo Antonio Tavella, Jonah and the whale, mid-17th. century

Cadence has had a long-chequered history in ESL, starting with the formation of the Alta group (where I used to work) in the mid-1990’s. After building Alta up to one of the biggest ESL groups in EDA, Cadence then wound it down through a series of “interesting” management decisions, eventually trading the remnant - primarily SPW - to CoWare who used it to broaden their scope of tools, and which provided a much more supportive environment. Cadence then went through a stage of denial, a stage of re-definition (trying, somewhat lamely, to redefine ESL as “Enterprise System Level”), and then embarked on some new R&D initiatives which have been kept mostly quiet for several years. One of these is in the area of high-level synthesis, and was discussed by Mitch Weaver of Cadence in 2004, as being a combination of Get2Chip behavioural synthesis technology together with Cadence Labs research, and with the promise that “Next year [... 2005 ...] you’ll hear some big news from us.” We had to wait another three years, but in April 2008 Mike Fister in a talk in Japan revealed more details about Cadence’s re-entry into “Upstream Design” (See “Cadence announces reentry into upstream design in Japan“). Here he talked about a SystemC-based high level synthesis tool which has been in evaluation in Japan for a year, and also alluded to other tools under the mysterious label “Sydney”.

Mentor Graphics has had a grab-bag of different tools in the ESL domain for many years including some they acquired when they bought Summit Design, but these have never been knit together into a common ESL toolset driven by a common design approach. Just looking at their website, we can see point tools such as their flagship high level synthesis tool Catapult, IP-based design assembly Platform Express, Visual Elite, and Vista (both from Summit) for capture and simulation in SystemC, a seemingly overlapping tool called System Architect, HW-SW coverification with Seamless (clearly now put under verification, along with the Questa tools), UML modelling with Bridgepoint, and the specialised automotive system design tool Volcano.

Chris Edwards drew an interesting diagram on one of his blogs illustrating the overlaps and complementary tools between Cadence and Mentor. (”Overlaps R US“). This shows Catapult vs. Project Sydney, although from Mike Fister’s comments in Japan, Project Sydney seems to have a wider scope. The other Mentor ESL tools, although not listed, seem complementary and not overlapping.  [UPDATE 22 June 2008:   Chris Edwards has updated his very useful chart to include several of the other ESL tools, and they are complementary, not overlapping].

So what will happen in ESL if Cadence buys Mentor? As I noted in the beginning, I’m no Nostradamus! No doubt the non-overlapping tools will be judged on a tool by tool basis to decide their worth as businesses and as technologies. With respect to Mentor Catapult vs. the Cadence high level synthesis project, no doubt the evaluation criteria will include relative market penetration and interest, quality of results, and the future of the technology as a basis for further development. The decision, of course, will be made by those in the combined company responsible for the ESL domain.

To start with, here is an image that will no doubt remind many of DAC:

Pieter Brueghel the Elder, Children’s Games, 1560

Although DAC covers many aspects of EDA, ESL and some focus on processors and IP, from my perspective I would say this was a DAC of ESL and multicore. I’m going to write on these two topics in more detail in other forums, but for now I would focus on two developments in each area:

ESL: 1. I heard from colleagues that there was so much interest in the Sunday workshop on High-level Synthesis that it was the best-attended workshop and the room was packed. I was not able to attend myself due to other commitments, but I also heard from others that they think the interest in high-level synthesis has been growing quite strongly and the use of it has been increasing.

2. The announcement by OSCI of TLM 2.0 now being available looks to be a significant milestone in ESL development. I have to still get back to the office and download the production kit and documentation to take a detailed look at the final product, but there were a number of ESL tool companies announcing support and quite a bit of user buzz about the capability, including an interesting user panel at the OSCI lunchtime session on Monday.

Multicore: 1. Interest in multicore at DAC has bifurcated into two areas: “Manycore” for EDA application using large servers or multicore processors scaling beyond 16 cores to 32, 64 +, and also using GPUs (Graphic Processing units from vendors such as NVidia). From Chris Malakowsky’s talk at the DAC Chairs reception Sunday evening to several technical sessions and presentations, this area is growing with real EDA applications ported to real machines and with quantifiable benefits in many parts of the design flow.

2. The other area for Multicore is the design of Multi-processor systems (e.g. MPSoC), including use of configurable processors. The SASP symposium on Sunday and Monday dealt in this topic and there were a number of very interesting sessions and panels that dealt with multicore SoC design. DAC is building a strong programme in this area.

I have enjoyed my time at DAC this week and am looking forward to next year in San Francisco in late July. To those who missed it, the proceedings and videos of some of the sessions and some of the many blogs about it should go some way to making up for missing it - but try to come next year.

Levels of Abstraction, by Frank Schirrmeister

As Frank points out in his blog, he drew this for Alberto Sangiovanni-Vincentelli back about a decade ago, and it has seen many incarnations since then. In fact, it has seen many many incarnations (I have now seen it in many talks and slides over the years, in a host of forms) - but usually without attribution. Although “reuse is everything” and “IP reuse” is to be encouraged, this should be done with due credit to the originators. So let’s see this slide or picture continue to propagate in many forms and variations……….but with proper attribution to its originator, Frank Schirrmeister. And someone I am proud to list among my friends and colleagues (and co-authors too). As a key thinker and do-er in the ESL domain, Frank deserves to be recognised for his contributions.

Please read Franks’ blog when you have the time, and give him comments. And please keep reading and commenting here!

“develop a multicore software programming guide for the industry that will aid in improving consistency and understanding of multicore programming issues.”

Even more interesting, for non-members, they are organising an informational meeting on the MPP initiative at the Design Automation Conference in Anaheim, on Tuesday June 10, from 1700 to 1830 (5-630 pm), room 201C in the convention centre. You should RSVP: see the Multicore Association website.

John Singer Sargent, Hercules and the Hydra (1922-1925)

On a related front, the end of May approaches and this should mean the appearance on the Multicore Association website of a publicly available version of MCAPI - their Multicore Communications API. Somewhat ironically, this was announced as being publicly available on April 1, but the news release just said it would “soon be publicly available” and the working group web page says it will be available by the end of May. Let’s hope so, as the public interest in MCAPI, and its possible takeup, will be a good indicator of whether the industry is beginning to converge on some standards here, as opposed to all the ad-hoc methods being used. The programming practices guide will hopefully give examples using MCAPI as well. Perhaps we’ll hear more about this in the June 10 meeting, which I also hope to attend. See you there!

Viktor Hartmann, Sketch of costumes for Ballet ‘Trilby’ (an inspiration for part of Mussorgsky’s “Pictures at an Exhibition”: Ballet of the unhatched chicks)

I was reminded of this conundrum while reading a press release from Synopsys (one of the pre-DAC runup in EDA-related press releases from many corners), on “Synopsys Adds 30 New Titles to DesignWare System-Level Library“, dated May 15, 2008. In this release, Synopsys discusses the addition of a number of transaction-level models to their SystemC libraries, including models of DesignWare IP blocks such as PCI Express 2.0 interconnect components, and processors such as PowerPC and MIPS.

The usage of system level models and virtual prototype or virtual platform models, in a number of tools including POSC (Plain Old SystemC), has long been felt to be gated by model availability. With this in mind, the availability of new models for components, especially interoperable SystemC models, but also including models with proprietary interfaces, is a good thing. The more models, the more likely it is that users of any of the tools out there will find models of existing IP available when they want to build system models of their complex designs.

All such developments will encourage more people to look into building system models, and the growth of use of system modelling (and the derivation of benefits thereby) will feed into a virtuous circle, where ESL modelling usage increases, encouraging demand for more models of components and IP, encouraging the growth in model availability, thus encouraging an increase in ESL modelling. Let’s hope that eventually the issue of model availability will become a secondary or tertiary issue in the growth of ESL modelling and usage.

Edgar Degas, Rehearsal of a Ballet on Stage

In the processor-centric design area, there is the co-located Symposium on Application-Specific Processors to be held June 8-9. On Tuesday June 10 there are technical sessons on Novel techniques in embedded processor design, a pavilion panel on Multi-processor SoCs: the next generation, and a technical panel on Multi-core SoC Design is the Challenge: what is the solution? On Thursday June 12 is a session on Multi-core Design Tools and Architectures.

In the ESL domain, as one might expect at DAC, there is much more going on. Sunday full-day workshops include the 5th International UML for SoC design workshop, and one surveying High-level synthesis. A North American SystemC users group meeting runs from 4-7 pm. Monday June 9 has an OSCI event at lunchtime, an OSCI Overview of TLM 2.0 in the afternoon, and a SPIRIT general meeting in the evening. On Tuesday June 10 we have a panel on ESL Hand-off: Fact or EDA Fiction. Wednesday and Thursday have many things going on - June 11 a lunchtime Mentor ESL symposium, a pavilion panel on Behavioural Synthesis, and a session on ESL methodologies for Platform based synthesis. One of the last sessions on Thursday is one on Design Space exploration, and the Thursday keynote is by Jack Little of the Mathworks offering “a different perspective on System Design”.

On the IP front there is a Pavilion panel Tuesday on IP Selection, and an interesting breakfast IP roundtable sponsored by Sidense on Wednesday morning at 8-9:30 am.

With all this, I have barely scratched the surface of the 45th. DAC. There are many more keynotes, panels, technical sessions, workshops, tutorials, special events dealing with all aspects of EDA and ESL, that you will find of interest. I hope to see you there. If you have other suggestions of other interesting sessions and events at DAC, please leave a comment here for all to read.

Claude Monet, The Artist’s Garden at Giverny, 1900

Among the many flowers we see in this garden are the Virtutech Simics kernel (an interesting article by Michel Genard on SCD Source discusses this: see Defining an infrastructure for virtual platform design). Virtutech is working with Greensocs on a Simics-SystemC bridge, according to Michel’s article. We also have OVP: Open Virtual Platforms, coming from Imperas, with a SystemC side door. ARM’s System Generator talks about a side door to SystemC in an NASCUG presentation by Nizar Romdhane. VaST has links to SystemC described in a white paper. And of course we have the single-kernel SystemC flower, planned to be supported by some ESL vendors - for example, see a NASCUG presentation from CoWare. (I will mention here that my company, and in some cases myself, work directly with some of these companies as partners, and of course, may with others in the list in the future).

One of the big issues I see in such a rich garden, and indeed, one especially important to IP providers, is whether models will interoperate among such a rich profusion of simulator architectures. If all the side doors or portals into the two-kernel simulation architectures conform to the same version of OSCI TLM2 Draft 2 interfaces, for example, then interoperability may become a lot easier. But this carries with it a potential performance cost. It may become very important “which side of the door” you live on. If a fast processor ISS model on the SystemC side of the portal wants to access memory which lives on the proprietary other side of the door, and if the portal between worlds does not support the OSCI Direct Memory Interface, then this ISS model may have to use slower mechanisms to access memory and thus be slowed down in comparison with the fast processor models living on the other side of the door. In the end, effective system modelling may depend on which side of the door you are. In this case, the door may become a kind of servants entrance: distinctly inferior to the main part of the house. And if everyone who has such a dual-kernel solution implements a different shape, colour or size door, then interoperability with each of these solutions may require a lot of extra integration effort. If this happens, our garden may become something a lot less pretty:

Alice Webb, Through the Thorns

We’ll have to see whether there is some kind of convergence on reasonably interoperable solutions for system modelling and simulation over the next few months. Given so many players, things could diverge. Of course, given good will and a drive for interoperability, things could instead converge. Hopefully, OSCI will play a leadership role in trying to keep our garden of roses from becoming a garden of weeds.

When I look at developments in ESL, I sometimes think of the painting and its title. Some of the old ideas in ESL must be good ones because they keep coming back. ESL synthesis, for example, has now been through at least two or three generations. In fact, to many people, ESL = ESL synthesis (or behavioural synthesis, or high-level synthesis). We have seen some recent activity in this area - for example, Celoxica got out of ESL synthesis to focus on FPGA-based accelerators for high performance computing applications, and moved its technology and team to Catalytic, forming Agility Design Solutions. At the recent Electronic Design Process Workshop, I saw Rishiyur Nikhil, CTO of Bluespec, give a talk on Parallel Atomic Transactions in the Bluespec synthesis approach. I’ve heard some people comment that they don’t really consider Bluespec (using System Verilog and some particular constructs to express their atomic transactions) to be “high-level” enough to be ESL synthesis. Most ESL synthesis tools use C/C++/SystemC or other dialects of C as inputs. However, the atomic transaction semantic used by Bluespec is definitely more abstract than the normal way people write HDL for RTL synthesis, so I think we can count it as among the family of recent high level synthesis approaches.

It was therefore interesting to read on the wire this morning of a new high level synthesis company called Fastpath Logic, with what they say on their very minimalist and unfinished web site is new ESL technology based on a new input language Chip Specification Language (CSL) for “chip and verification infrastructure generation”. They describe this task as being different from, and complementary to, the creation of the algorithm implementation (which has been the focus of most ESL synthesis up till now). It will be interesting to see exactly what is entailed in CSL, and what the interface generation will provide, and how it will complement the use of RTL or other ESL synthesis approaches for algorithm implementation. No doubt more will be revealed by the time the Design Automation Conference (DAC) rolls around in Anaheim June 12-18. I don’t see Fastpath Logic on the list of exhibitors as of today (April 24, 2008) but perhaps someone from there will be wandering the DAC floor and people may run into them.

Hope springs eternal in the ESL arena….

Taxonomies of this kind have been useful in EDA and ESL in the past - I think of the RASSP and VSIA work on model taxonomies that at one point was the most widely downloaded VSIA reference document. It would certainly be useful if everyone recognised a common definition for “multicore” when they hear it (2 cores? 4 cores? a few but less than 32? symmetric? cache-coherent?), or “manycore”….

As most people in industry may be too biased by their particular corporate inclinations (and I concur that I am too!), this would be a great thing for an academic to set up as a web site to which many could contribute - maybe a Wikipedia of the Multicore world. Perhaps a vigorous discussion by interested industry and academic people could lead to a consensus………perhaps not! But it might be worth trying.

While we were at it, it would also be a useful place for people who have successful examples of parallel or concurrent programming on multicore or mapping examples to homogeneous or heterogeneous multiprocessor systems to be able to list them there. This would be valuable for all who are new to this area who don’t have all the right history in the field that a lot of the HPC (high performance computing) people have, for example.

Is there someone in academia who could take the lead on this? I’m hoping….

Working in Santa Clara, I have begun to think of the Santa Clara Convention Centre, which is about a mile or so from Tensilica, as in some ways fulfilling the functions of a local, at least when there is a relevant conference going on there. They often have receptions at such conferences, usually on an exhibit floor, and there may well be some good food and beer on offer at these receptions. These receptions also meet some of the other criteria for a good pub: a chance to meet old friends and colleagues, to make new friends and colleagues, to get new gossip and possibly information, to swap stories, etc. It may lack the more intimate surroundings of a good pub, but still offer a fun experience.

Last week (March 31-April 3) there were two interesting and overlapping conferences at the Santa Clara Convention Centre: SNUG (the Synopsys User Group) and the MultiCore Expo. Both had a lot of interesting content and quite reasonable attendance. (Both also had good receptions!) But one interesting thing I noticed relates to ESL.

For many years, ESL has been talked about a bit like the Once and Future King: always on the horizon, never quite there, always promising, never being used. Of course, as I have commented on before, this may be partly due to your definition of ESL, and they do vary widely.

What I noticed in one session in SNUG, where Filip Thoen of Synopsys talked about a virtual platform case study, and in many sessions at the Multicore Expo, including the panel I was on talking about virtual platforms, was that the Existential question about ESL seems to have gone away…..at least, if your definition includes the use of system models and what are called ‘virtual platform’ models for architects and software developers. Richard Goering, who chaired the Multicore Expo panel on virtual platforms, asked the audience how many had or were using these kinds of models. I noticed about 15 hands go up. Although Richard in his article on SCDSource (http://www.scdsource.com/article.php?id=164) called that “only a handful”, from my perspective, that is a much bigger handful than it would have been a year ago, and I expect in another year that it will be two or more handfuls in such a venue.

In other words, I think we can stop debating the Existential questions about ESL: it exists, it is being used, and the real debate should be about the particular methods, tools, models and approaches that are most useful.

Funny what you can find out down at your local……………..