Taken for Granted

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Book Review: TLM-Driven Design and Verification Methodology

Filed under: Uncategorized — October 10, 2010 @ 3:16 pm

In late July I received a copy of a new book published by Cadence:   TLM-Driven Design and Verification Methodology.   I should mention up front that I know four of the authors well:   Brian Bailey, Felice Balarin, Mike McNamara and Yoshi Watanabe.   The other two authors are Guy Mosenson and Michael Stellfox.

The book is available from Lulu in a print-on-demand form here (price $US 110.99, for the physical book); from Amazon electronically for the Kindle here (digital list price $US 84.99, although selling for $77.21 on Sunday October 10 when I checked); and from Amazon in paperback form here (list price $110.99, but selling for $85.79 on Sunday October 10).   You can read more about the book and other people’s comments on it at the Cadence web site here.

It is part of a growing trend of corporate-sponsored technical books being made available in new forms such as print-on-demand and electronically, rather than via conventional publishers.  Other examples of this trend are two other books  – one from Cadence, one from Mentor Graphics:

  • A Practical guide to Adopting the Universal Verification Methodology by Sharon Rosenberg and Kathleen Meade.  You can read about it here.
  • High-Level Synthesis Blue Book, by Michael Fingeroff.  You can read about it here.

As corporate-sponsored books, they of course will feature the sponsoring company’s tools in giving examples of the methodologies they discuss.  This is of course both natural and to be expected – illustrating the concepts in action is valuable, and they have to be done with some tools whether academic or commercial.    I have used Tensilica’s tools and IP  as examples in several chapters in several books, most notably in my recent book co-authored with Brian Bailey, ESL Models and their Applications:  Electronic System Level Design and Verification in Practice, from Springer.

I should also mention that I was not very quick in reading the TLM-Driven Design book, taking over two months to finish it.   The only thing I will plead is pressure of work, which also explains my small number of blog posts over the last year (see Too Busy to Fulminate).

So on to the book.   First, it is well-done:  well-written, nicely laid out, with excellent colour drawings and screen shots (some of which are just a little too small for my aging eyes, but readable when I looked closely), and high production values.  My review copy may not have been quite the final version but it was nicely done all the same.

Second, it contains a lot of good methodological advice, both in explicit chapters and sprinkled throughout.  As someone who has long believed that design methodology comes first and good tools come second, it was gratifying to see this focus.  Although the methodology is implemented in detail with Cadence tools, many of the steps involved in the implicit and explicit design flows can be accomplished with competitive commercial,  academic or internal tools.   One good example:   chapter 3 describes five levels of abstraction in the TLM methodology:  pure functional, Functional Virtual Prototype (FVP)-ready, High Level Synthesis (HLS)-Ready TLM (Transaction Level), HLS-Ready Signal Level, and RTL.   Following much of the design flow through these various levels can be accomplished with (mostly) Cadence tools, or can be accomplished with a set of tools without anything from Cadence in them.   This is a good example of a design methodology that goes beyond a particular set of commercial tools.

As a result of a focus on methodology, there are some very useful lessons and points contained in this book that should be of interest to the general electronic design community, going well beyond those who are Cadence tool users.  The preface and the first three chapters – preface and  chapter one with an overview of design issues and processes, needs and requirements, and attributes of a TLM-based methodology; chapter two with an overview of languages for TLM; and chapter three with an overview of the Cadence TLM-driven methodology – will be of general value to a wide readership.

The heart of the book is chapters 4 and 5, on high-level synthesis, and the supporting Appendix A on the SystemC synthesisable subset.  Chapter four is a good overview of high-level synthesis fundamentals (that is the name of the chapter).  Chapter 5 goes into considerable detail on the Cadence C-to-Silicon Compiler tool with worked examples to illustrate how the tool works and what it can offer designers.  As well as dataflow examples, this chapter also gives some insight into control oriented HLS and also using HLS in ECO (Engineering Change Order) design – that is, incremental modification of a design and how that is reflected in a tool flow.   This latter has not been addressed much in most writing on HLS.

Although chapters 4 and 5 have a good set of references, one additional one that is a useful overview of HLS is the book edited by Philippe Coussy and Adam Morawiec:  High-Level Synthesis: from Algorithm to Digital Circuit (Springer, 2008).

I was disappointed in Chapters 6 and 7, which conclude the book.  They are both on verification – chapter 6, Verification Fundamentals, and chapter 7, TLM-driven verification flow.   They cover Cadence verification tools in the context of the UVM – Universal Verification Methodology.   They are somewhat repetitive, in going over similar ground twice.  It might have been better to recut these two chapters into two on verification with the methodology and the practice using Cadence tools a little more blended.  This could have reduced some of the repetition.

One other aspect of these latter two chapters is that I could not get a strong sense of the relative advantages and disadvantages of the two primary languages used and illustrated – e and SystemVerilog.   Cadence has been fence-sitting for a long time on the verification language issues – somewhat naturally, given its acquisition of Specman and e, and the desire to evolve its tools to support SystemVerilog.   As is acknowledged in chapter two, this book is more e-centric, perhaps reflecting a desire by Cadence to reinforce its strong position with this  still mostly proprietary language (it has an IEEE standard, 1647, but is still primarily supported by Cadence).  A little more clarity on these points would be useful but perhaps too much to expect from this book.

However, these are relatively small quibbles.   Overall, the book is most useful for its general guidance on modern methodologies, and its good overview of HLS and the Cadence C-to-Silicon HLS tool.   If you are interested in modern TLM-based design approaches, I think this is well worth a look.

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