Taken for Granted

ESL, embedded processors, and more

Day 3 of DAC 2010: Snatching Victory for NOCs from the Jaws of Confusion

Filed under: Uncategorized — June 17, 2010 @ 10:35 pm

On Wednesday June 16 I moderated a special session at DAC 2010 in the morning: “A Decade of NOC Research – Where Do We Stand?”.  This was an extremely interesting special session, organised by Anand Ragunathan and Sri Parameswaran, with three excellent speakers:

  1. Giovanni De Micheli of EPF Lausanne, Switzerland, who gave an overview of NOCs (Networks on Chips):  “Networks on Chips:  From Research to Products.
  2. Kees Goossens of TU Eindhoven, the Netherlands, who talked more deeply on “The Aethereal Network-on-Chip after Ten Years:  Goals, Evolution, Lessons, and Future”
  3. Bruce Mathewson, AMBA architect and Fellow at ARM in Cambridge, UK:  “The Evolution of SOC Interconnect and How NOC Fits Within it”.

Each talk was highly informative and entertaining, and the sum of the three gave a really good view of NOC past present and future.  The up to 90 people in the room seemed to agree.   Each talk had questions, and then we concluded the two hour session with a panel discussion of 30 minutes on relevant NOC questions.   The audience provided every question (I took the opportunity to lob in one of my own, but it was not necessary) and there was an excellent debate on NOC.

Kaist NOC research chip, Korea

Kaist NOC research chip, Korea

One issue that came to the fore in the talks and panel discussion is that the definition of NOC is extremely elastic.   It can be defined by characteristics, but many of the attributes of a NOC have been influential in advanced hierarchical bus style interconnect such as the relatively recent AMBA4 by ARM.   As a result, I would suggest it is time to think of retiring the NOC term and use “advanced interconnect” instead.   Future complex SOCs will use interconnect that incorporates attributes and concepts drawn from buses, point to point interconnect and NOCs and may have several different styles used in different subsystems,  with a chip-level interconnect concept suitable to the application.   Thus perhaps without having very many commercial examples of chips that are “pure NOCs”, we can declare victory, retire the term, and move onto the more important issues of specifying, designing and verifying the complex interconnect schemes that future designs will need.

A second interesting issue is the growing importance of tools for designing advanced interconnect for SOC, whether bus or NOC based or mixtures of all types.   In the past design groups could muddle through evolving from legacy buses, but this looks less likely in the future and NOCs in particular need modeling and analysis tools to make sure they are right for the application, and implemented with the right characteristics.  The EDA industry in particular seems to be letting the side down here, as the panelists and audience did not see EDA/ESL vendors offering anything much in this domain.   At a crucial time for the EDA industry and with major changes afoot, highlighting this future opportunity at DAC sounds like the right thing to do.

My thanks again to the organisers and speakers.  It was a great session of high value to all who attended.   I was glad that I was asked to help out.

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