Virtual Consolidation
It has now been more than a week – time for the dust to settle a little bit, on the news from two weeks ago and last week that Synopsys had acquired VaST, and then CoWare; and that Intel had acquired Virtutech and was planning to merge it into its Wind River subsidiary.

Several commentators have talked about these acquisitions, including:
- Paul Mclellan on VaST, Virtutech and CoWare
- Brian Bailey on VaST, Virtutech, CoWare, and additional comments here.
- Gabe Moretti on VaST and more generally on Synopsys and virtual prototyping.
- Clive Maxfield here.
The books ESL Design and Verification: a prescription for electronic system-level methodology, and ESL Models and their Application: Electronic System Level Design and Verification in Practice, which I co-wrote, both deal with virtual platforms and prototyping in some detail.
Bill Murray in SCDSource had a couple of excellent writeups on virtual prototypes in late 2007 and early 2008: Virtual Platforms – a reality check, Part 1 and Part 2.
It’s of course too early to know what the specific plans Synopsys and Intel (Wind River) have for the technology they have acquired and the people working on it. But there are a couple of comments worth making here:
- the three V’s of virtual prototyping – Virtio, VaST, and Virtutech – are gone or will be going. For fans of alliteration, this is a great shame.
- More important is to speculate on what the companies might do with the technology in this domain in the future. As discussed in the two books I reference above, there are many use models for system models and virtual platforms. Some of these are offered by the commercial tools, or at least some of them. Some tools offer only instruction-accurate (fast functional) system modelling; others offer both that and cycle-accurate system and component models. Both levels have their uses and the modelling approaches also vary. Will consolidation lead to more complete sets of model offerings?
- In addition, one big gap that I see in virtual prototyping is to bring it together with particular software development methodologies and tools to give users a faster and better way to carry out multicore partitioning onto heterogeneous or homogeneous clusters of processors, and thus move more rapidly to a partitioned system architecture. The virtual prototypes allow you to simulate the results of decisions but partitioning software onto multiple processors, setting up communications libraries and methods between them, and modifying the software to accommodate different mappings, is still a fairly tedious manual process. Might the consolidated resources of some of these companies allow them to make advances in this area?
As always, I welcome your comments.
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October 31st, 2011 @ 5:00 pm
I realize that it’s been 18 months but better late than never, on #3!
Grant, please check out Space Codesign, we’re a university technology transfer spin-out from Ecole Polytechnique de Montreal that has productized hardware/software codesign developed in the GRM2 lab, lead by Guy Bois.
http://www.eetimes.com/electronics-blogs/other/4230225/Tool-tackles-hardware-software-codesign-for-ARM-based-FPGAs
Our initial target is FPGA but our platform is scalable and we will be working with ASIC flows as well.
October 31st, 2011 @ 6:55 pm
Gary
Whether 18 minutes or 18 months, any comment is welcome anytime! Actually, if you ask Guy, he knows me quite well as I know him. In fact, Brian Bailey and I got him to write a considerable section in our book ESL Models and Their Application: Electronic System Level Design and Verification in Practice. (see http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-0964-0) In chapter 7, “Codesign Experiences Based on a Virtual Platform”, there is quite a bit about Space CoDesign. And I knew quite a bit about Space Codesign before it spun out of Ecoly Poly.