Taken for Granted

ESL, embedded processors, and more

Day 3 of DAC 2009: Virtual Platform Workshop

Filed under: Uncategorized — July 30, 2009 @ 12:15 am

I was able to attend two parts of today’s all day Virtual Platform workshop at DAC.  Before getting into it, I would like to relate a comment from a colleague – he was surprised and grateful that there was such an event at DAC because he had not expected to see a full day event at this point dedicated to such a new area.  I think it is commendable that DAC accepted the workshop proposal and that the organisers put in the effort to make the proposal and then organise the workshop.

A non-virtual platform

Soha Hassoun of Tufts, one of the two organisers, opened by saying she spent a sabbatical at Carbon Design Systems and was intrigued by virtual platform technology and made the suggestion of a workshop to DAC.   When it was accepted, she enlisted Larry Lapides of Imperas to help organise it.

There seemed to be about 30-35 attendees during the periods I attended.  Perhaps if this is repeated in the future, the attendance will grow, in line with the growing interest in ESL and virtual prototypes.

There were several interesting talks I saw.  Two in particular were:

  1. Oliver Bringman, FZI; J. Gerlach, Bosch, U. Nadeldinger, Infineon, J. Stellmacher, Cadence:  “Modelling, Analysis and Refinement of Heterogeneous Interconnected Using Virtual Platforms”.  This was based on the VISION project in Europe, a collaborative between the multiple parties, that built a platform based design flow centred on UML profiles derived from extending SysML and MARTE, as well as using XML descriptions of components similar to IP-XACT (but extended), and tools that allowed mapping of function to architecture, platform refinement using protocol adapters and parameterised platform templates, and finally the generation of virtual platform models.  This was a sophisticated piece of work and it was interesting to see another use of UML to build a flow.  They also had good advice on how and where to use UML (at higher levels – e.g. platform composition at transaction level) and were not to use it (e.g. to build an RTL level flow or cycle accurate models).
  2. Qi Zhu, Michael Kishinevsky, Zhu Zhou and Atul Kwatra, Intel, “Architectural/Micro-architectural exploration on virtual platforms”.  This was a pretty advanced use of SystemC 2.2 and TLM 2.0, along with AT (approximately timed) models, and internal tools – eg. to validate TLM models – to build an internal modelling and exploration flow.   It is interesting to see how a company like Intel, with large internal resources, built a tuned set of tools, models and flows to match its own requirements without using commercial tools – and to see the pros and cons of the approach.

A final comment – I ducked out of the keynote to attend part of the Mentor Graphics 7th. ESL Symposium Lunch and Panel – where Alan Su of Global Unichip had an excellent quote about ESL:

ESL is no longer a trend, it is a reality – if you don’t use it (in your design teams), you are doomed.

I think the Virtual Platform workshop accomplished the objective of pointing a way awy from doom and towards reality that many design teams can benefit from.


  1. Taken for Granted » DAC 2009 Wrapup: The end of ESL ExiStentiaLism?:

    [...] experience, and those of many others, indicates that system level modelling is very real (see the virtual platform workshop at DAC 2009 for the first time), it is time to move from the almost childish debate about whether ESL is real [...]

  2. SKMurphy » DAC 2009 Blog Coverage Roundup:

    [...] Grant Martin on “Virtual Platform Workshop at DAC” in “Day 3 of DAC 2009: Virtual Platform Workshop“ [...]

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