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DAC 2009 Preview

Filed under: Uncategorized — June 17, 2009 @ 3:48 pm

This year, I thought that I might not make it to the 2009 Design Automation Conference, even though it is back in San Francisco, my back yard, so to speak. This is because during the previous two weeks I will be on a busman’s holiday at a summer school, teaching at ACACES 2009, and giving a talk at SAMOS 2009. However, I am fortunate that I will be able to attend a fair bit of DAC and will be writing about it on this blog, just as I did for DATE 2009.

With the logistics taken care of, what is there to see and do at DAC? The answer, as with DATE and other medium to large conferences, is two-fold: Lots! and perhaps Too Much! There are a large number of parallel activities with parallel technical sessions, panels in the exhibit, workshops, tutorials, co-located events and ancillary meetings and events. If you graze through the advance programme (Sunday-Friday) pdf, you will find a cornucopia or smorgasbord of tasty treats. Here are just a few of many that caught my eye:

  1. The Sunday workshop on Multiprocessor System-on-Chip: Current Trends and the Future
  2. Also on Sunday, the 6th. UML-SOC workshop
  3. On Monday and Tuesday, a colocated event – the Symposium on Application Specific Processors (I am helping to organise part of it)
  4. On Monday from 1-2 in the Exhibit, a Pavilion Panel: Hogan’s Heroes: The Long Road to System Level Signoff
  5. The Monday tutorial on High Level Synthesis
  6. A Monday Exhibitor Forum on Architectural Exploration from 10:15 to 12:15
  7. Also on Monday (do you see what I mean about parallel events??) the North American System C User Group meeting from 11:30 to 5.
  8. A Tuesday Panel from 10:30 to 12 on System Prototypes
  9. A Tuesday Pavilion Panel from 3:30 to 4:15 on Embedded Multicore: Multi-Opportunities, Multi-Challenges
  10. A Tuesday technical session on Advances in Embedded System Modeling and Optimization from 4:30 to 6 pm
  11. The Wednesday workshop on Virtual Platforms
  12. The Wednesday User track session from 4:30 to 6 on Front-End Development: Embedded Software and Design Exploration
  13. Bill Dally’s Wednesday keynote from 11:15 to 12:15: The End of Denial Architecture and the Rise of Throughput Computing
  14. Also on Wednesday, not on the DAC programme, Mentor Graphics is hosting a lunchtime ESL event: ESL Driving Forces: The Art of Architecture Design and Verification. (You need to preregister at the link).
  15. On Thursday, the panel from 4:30 to 6 pm: The Wild West: Conquest of Complex Hardware-Dependent Software Design
  16. A technical session on Thursday from 2 to 4 pm: Network-On-Chip Advances for Power, Reliability and the Memory Bottleneck

Whew! That’s enough for now! My calendar is hardly filled and I’m already tired! And there will be interesting exhibits too, especially from new exhibitors. But I think you get the picture.

If anyone else has looked through the DAC 2009 prorgramme and has other suggestions, feel free to leave a comment.

3 Comments »

  1. Samta Bansal:
    June 25th, 2009 @ 12:03 pm

    Grant, great list !! Thanks.
    However, there is one demo that you and your readers wouldn’t want to miss :-) ====================================================
    Architectural Prototyping: Don’t scrap or delay a project because of cost issues !!

    Bring Architectural predictability to your Design cycle upfront !!

    It is about how we are changing the way people think and do designs. As you know 80-20 rule in design cycle management still applies – 80% of a product’s cost is determined in the first 20% of that product’s development cycle. But guess what -The system architects making those cost estimates and implementation engineer who actually designs the chip sit in two different worlds with least information exchange to do effective product realization with minimal risk. You almost always leave money on the table because of this gap between them.

    So Cadence has come up with an innovative way to bridge this gap and help mitigate the risk involved in this current design planning process. A never seen before breakthrough approach that provides visibility throughout design process from IP selection to implementation and signoff.

    We will be showcasing this unique capability through an “On demand” demo at ChisEstimate.com booth and at Sales Suite at Cadence booth. This Demo would walk you through a methodology to close the feedback loop and provide a new and better way of doing design for both system architects and implementation engineers.

    To learn more, please read the recent announcement we did along the same lines:
    http://finance.yahoo.com/news/Cadence-Unveils-Integrated-iw-15462623.html

    and now is the time for our customers to actually see it. So please come by and ask for this demo at ChipEstimate.com or Cadence booth !!

    =====================================================
    Who should Attend: System Architects, Design Managers, Implementation Engineers

    Which Products showcased: Incyte, EDI System

    ======================================================

  2. Grant Martin:
    June 25th, 2009 @ 12:15 pm

    Normally I might have spammed a commercial such as the comment above, but since the blog was a DAC preview, and since the exhibitors are a full and important part of DAC, it seems useful to the readers of this blog, whoever they are, to let comments highlight things they might find useful in the exhibit. We’ll see if there is a flood or a trickle! Thankfully, there is some moderation possible…..

  3. Ran Avinun:
    July 10th, 2009 @ 1:13 am

    Grant,
    Nice coverage for the ESL activities at DAC. Cadence has organized and is participating in many activities at DAC this year. One of the highlights is going to be a system lunchoen panel (sponsored by Cadence, Calypto and Forte) called “Are SystemC and TLM-Driven Design Ready to Replace RTL?” on Tuesday July 28th between 11:30am and 1:30pm in room 306-308 – in this luncheon, you will hear from vendors and users about the changes happening in the industry in this domain.

    I summarized all the system activities, Cadence is involved, in my blog at:

    http://www.cadence.com/Community/blogs/sd/archive/2009/07/06/Cadence-System-Design-and-Verification-at-DAC-2009-.aspx

    Ran Avinun
    Cadence Design Systems

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