Taken for Granted

ESL, embedded processors, and more

Is DMA an MoC?

Filed under: Uncategorized — May 8, 2009 @ 2:15 am

Something that has interested me the last little while is the whole area of DMA (Direct Memory Access) and its role in multiprocessor/multicore systems, streaming multimedia applications, and the like.   DMA controllers are often programmed at a pretty “close to the metal” level, without a great deal of abstraction.   Sometimes looking at tasks with DMA transfers programmed in close to algorithmic code with DMA programmed by setting registers to obscure hex values obscures what is actually going on.

DMA to memory on a local node from an SGI publication

In addition, DMA seems to be a different “MoC” (Model of Computation) than other ones I am a bit familiar with, such as SDF (Statically scheduled dataflow) or Discrete Event (DE).  In a dataflow model, tokens arrive at input ports for an “actor” and when enough have arrived according to defined constraints, the module fires, running to completion and producing output tokens.  DMA seems to me to be “anticipatory dataflow”, where a task running perhaps on one processor finishes enough of its processing on some data, producing outputs to be handed off to another processor and its task for further computation, but does not wait until it has totally run to completion but uses DMA to transfer tokens in anticipation of the need for them by its counterpart.   Rather than using for example FIFO channels to transfer tokens, DMA uses other mechanisms such as ping-pong buffers in destinations and more elaborate DMA controllers allow transactions to be added in flight.   To avoid blocking, it is important to anticipate when a transfer can be consumed (thus, ‘anticipatory’) and to avoid starvation, it is important to send data when needed.

I’ve done informal and cursory web searches to find out what abstractions people might be using to make DMA programming a littler easier, and actually not found much, other than some Microsoft CE APIs from several years ago.   Are there defined APIs for DMA in widespread use and not specific to particular controllers and SW stacks but generic and configurable enough to be used on different targets?  If anyone has a pointer to the same, please leave a comment.

2 Comments »

  1. Jakob Engblom:

    can’t you say that DMA is really just an assembly-language implementation of dataflow? It is just the mechanism to move the data, but the important thing is that data moves from A to B? The overlap of computation and data transfer is just pipelining, at a system level? Just like a CPU pipeline implements a supposedly serial instruction set in a parallel fashion?

  2. Grant Martin:

    Jakob, although the DMA I have seen used in real life is a bit like dataflow, it seems a little more complex than that. Consider processor A doing computation on data items 1,2,3….and passing the results 1A, 2A, 3A, …to B via a ping-pong buffer in B’s local memory using DMA. B works on 1A, 2A, 3A… and passes them back to A via a different DMA ping pong buffer in A’s local memory – using the same central multi channel DMA engine. The ping-pong buffers are different than dataflow queue buffers – ideally you want some kind of balanced system where A knows just when it can and should send something to B, and B knows the same. This kind of scenario strikes me as even more prone to deadlock than finite FIFO data flow, and so I wonder if some additional analysis methods would help in designing this (without being an expert on MOCs!). I can raise the questions, but wonder whether someone else can point to some solutions.

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