Some of those who read this blog may recall a post I wrote last November, entitled “The Myths of EDA – the 70% rule”, about the oft-stated claim that Verification takes 70% of the effort in a design project. I was at the North American SystemC User Group meeting (NASCUG) at DVCon today, and ran into my friend Frank Schirrmeister from Synopsys, who said that a recent study by Synopsys and IBS had reviewed 12 design projects and produced some new statistics on the effort. Furthermore, Frank has written this up in a Synopsys online newsletter article, entitled “Increasing Verification Efficiency using Virtualization and Reuse of System-level models”. I suspect Frank will also add this to his blog and it is certainly useful to see updates on these kinds of design methodology statistics.
I’ll try to write up my observations of the NASCUG meeting soon….
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