Taken for Granted

It is a truism in Silicon Valley and most other places where engineers congregate, that if you want to get a good crowd out to an event, offer them a free lunch.  The Low Power Design Summit, sponsored by Cadence’s Power Forward Initiative, and held on Wednesday October 1 at Cadence, San Jose, was no exception.

Pieter Brueghel the Elder, The Peasant Wedding, 1567-1568

However, in this case, seeing the large crowds (at least 200 people during the day by my quick reckoning, sometimes in one room and sometimes split into two tracks) and the number of questions asked during some of the presentations, I think it was a toss up between the interest in low power, and the CPF and the tool flows from Cadence and other tool suppliers that support it, and the interest in a free lunch!

One thing that is pretty likely in events of this kind is a fair degree of marketing as opposed to purely technical presentations.  However, this can still be quite useful to give an update on various technologies and how they are being used, and a fair trade for the attendees’ time as long as the event is free.  There were a number of nuggets presented during the day that rewarded attendance.  (Another thing I enjoyed was the chance to help fill in the Cadence history chart in their cafeteria with some items of Alta history from the late 1990s).

It was clear from the presentations from many IP suppliers and users are applying CPF in a very practical way.  It was also interesting that the other Elephant in the room (perhaps not the best analogy since there the US elections are on right now) is the competing UPF format.   It was only in the morning panel when Ameesh Desai of LSI mentioned the competing UPF format (and the extra work involved in supporting both) that the other Elephant was acknowledged.   It is also unclear what the usage status of UPF among real users and IP suppliers currently is, although I am sure the UPF supporters will continue to talk about that.

Perhaps the most interesting part of the day was the morning panel “Deploying Low Power - What are the Challenges?”, moderated by Susan Runowicz-Smith of Cadence and featuring Ameesh Desai of LSI as noted, Anis Jarrar of Freescael, Herve Menager of NXP and Brani Buric of Virage Logic.  One of the things I was most interested in were the questions and discussions of whether system level was being added to the low power flows, and whether work was progressing on filling in this gap.  A very interesting perspective on this was the question:

How much better than Excel can a system level power tool be?

The gap was acknowledged, but the way forward seems unclear.  Perhaps readers may have comments on how to fill in the system level power gap in the flows.

Near the end of the afternoon, Carl Guardino of the Silicon Valley Leadership Group gave a quick talk on Green initiatives and prospects in the Bay area.   This was very interesting and the SVLG gave out booklets “Clean and Green” , their 2009 Silicon Valley projections covering the environment, energy, transportation, workforce, housing, health care and tax policy.  My favouriite wish - BART to the south bay, was covered along with many other ideas, initiatives and projections.  You can download and read the plan at the links.  Perhaps the best quote in the whole day was one Carl Guardino repeated from David Packard, who helped found the Silicon Valley Leadership Group 30 years ago - this should be a watchword for us all:

When you do something well, don’t gloat about it. Go out and find something harder and better to do.

The organisers promise to have versions of the presentations posted at Power Forward soon.