The Cadence C-to-Silicon Compiler uses RTL Compiler to validate that each part of the RTL description CtoS is building will meet the specific area, timing and power goals of the design team, as well as whether the entire circuit will meet the QoR requirements when implemented as gates by RTL Compiler with the chosen technology library and clock speeds. This automated flow enables CtoS to leverage the powerful optimization features of RTL Compiler’s global timing, physical aware synthesis, rather than perhaps fighting with it.

Customers are free to, and have taken the CtoS generated RTL through other implementation paths; the results are just not as correlated with the model of implementation that CtoS used when it chose the RTL structure and particular sharing and timing relationships. Our RTL works with all flows, but works better with the Encounter RTL Compiler flow.

As Dan suggests, one gets better results if you can “see over the horizon.” Consider a golfer hitting out of a deep sand trap – some might get lucky and hit the ball into the hole – but most would get better, more consistent results if they could somehow model the entire flight of the ball, including the selection of the putter to be used for the next shot. (So yes, we are taking the fun out of the game of chip design, and making it a boringly predictable enterprise)

Your observation that Cadence’s C2S goes all the way to gates via the embedding of RTL compiler is an interesting one. Cadence implied that for control, this improved results; but I am not sure whether this is really the case for the dataflow applications that many of the other ESL synthesis tools seem to have been concentrating on. But I agree with you that QoR is vital, and it would be fascinating to see comparative benchmarks of different tools running on several applications. Certainly it is good to see the announcement of a development by Cadence in the ESL space (and a development that was telegraphed many years ago and that people have been waiting for).

Grant

One point you might have overlooked – with the attempted hostile takeover of Mentor by Cadence, could Cadence be contemplating spinning out the C-to-Silicon team (maybe merging with Calypto?) to avoid the regulatory issues they cited (overlap with CatapultC)?

I think one of the key’s of Cadence’s announcement is the fact that they are the FIRST ESL VENDOR to offer a C-to-GATES solution … everyone else believes C-to-RTL is adequate, and it’s not. Users will not adopt a ESL flow that does not deliver adequate quality of results (QoR) – what sense does it make to increase productivity if product quality declines? That is, who in their right mind would adopt a design flow that produces more gates, consumes more power and offers less performance? I know of none.

So, QoR is vitally important … and that’s what I believe is the hidden gold nuggest in the Cadence announcement. By embedding RTL Compiler, they can deliver competitive QoR AND eliminate the need for a user to have a Synopsys DC tool/license.

It’s a very shrewd move by Cadence – kudos to Mac, Steve Carlson and the rest of the crew at Cadence.

Maybe it also takes a decade to break a market stranglehold like Design Compiler has had … Mentor
did it to Cadence with Calibre, can Cadence do it to Synopsys with C-to-Silicon?

Dan

BTW: Enjoy your blog pics. Remind me of the EETimes old “Immortal Works” contest pics. Cheers.