Taken for Granted

ESL, embedded processors, and more

Leibson’s Law in Action? Cadence returns to ESL with new synthesis tool

Filed under: Uncategorized — July 14, 2008 @ 2:03 pm

My colleague and friend Steve Leibson writes a blog for EDN, “Leibson’s Law”, in which he discusses many items relating to his informal law:

Leibson’s Law: It takes 10 years for any disruptive technology to become pervasive in the design community.

In this case, I wonder if Cadence’s announcement today (July 14, 2008) that it has returned to the ESL Synthesis arena with its new C-to-Silicon Compiler tool, along with the corollary announcement from Calypto about linking their SLEC System-HLS tool with the new Cadence tool, is a case of Leibson’s Law in action.

Rembrandt van Rijn, The Return of the Prodigal Son, 1669, The Hermitage Museum, St. Petersburg, Russia

There are good writeups about this new tool that was done by an incubator team under the name “Project Sydney” that contained several people from Cadence Labs, Berkeley. Two on the web are by Richard Goering at SCD Source and Ron Wilson at EDN. (It was also telegraphed conceptually a week ago by Mike McNamara in an article “ESL Handoff: closer than you think”, on EDA DesignLine online). Among the features discussed as part of this new tool are an ability to deal with design hierarchy, an ability to mix control and dataflow to new levels, incremental synthesis, and an embedding of Cadence’s RTL compiler or a subset of it in the tool to improve results, especially for control. I will be interested to see more about user reaction and evaluations of the tool, but note that Cadence, Renasas and Hitachi have worked together on the tool for a significant period prior to today’s announcement. It will also be interesting to see how it fares against the competition from Mentor Catapult, Forte Cynthesizer, Synfora, Bluespec, AutoESL, and others in the high-level synthesis field, which is relatively crowded at this point.

More interesting, perhaps, on a higher level, is what this return of Cadence to ESL design (not “Enterprise System Level”, but real ESL design) means for ESL in general. It is now a decade, give or take a couple of years, since Cadence absorbed its pioneering Alta Group subsidiary back into the Cadence main stream. It is coming up for 5 years since Cadence moved what was left of its pioneering system-level tool team over to CoWare. If Cadence’s return to the ESL design arena is an indicator that ESL has begun to enter a mainstream phase (or as Leibson’s Law would have it, begin to become pervasive in the design community), then that is a good marker for ESL and adoption. Coming after last week’s announcement that Carbon Design Systems was picking up the SOC Designer tool and much of the development team from ARM, thus breathing new life into that tool, these signs of change in ESL may be welcome signs of mainstreaming.

As usual, “time will tell”!


  1. Sean Murphy:

    This is a very useful summary that places several announcements in context. What I appreciate in particular is that you linked to the source material on-line, regardless of where it came from, in a blog that’s nominally sponsored by Chip Design Magazine. You have links to EE Times, SCDSource, EDN, and Chip Design Mag. I do think we are seeing the emergence of viable products at design abstraction levels above RTL (my suspicion is that what we now refer to as ESL will be divided into at least three layers). McNamara’s article was also important, as you correctly point out, because it abandoned Cadence’s earlier effort to redefine ESL as “Enterprise System Layer” and return to working within the commonly understood context of the term.

  2. John Blyler:

    Great blog, Grant! You should pass it on to StanK, who returned to Cadence just a few years ago after departing shortly after Cadence sold off their previous ESL program.

    BTW: Enjoy your blog pics. Remind me of the EETimes old “Immortal Works” contest pics. Cheers.

  3. Dan Ganousis:

    Nice summary Grant. In January I posted an article on SCDSource regarding why ESL vendors were having a difficult time increasing their valuations. I offered that a “rollup” of ESL vendors was imminent – and as you point out, it appears to be in process (Carbon’s acquisition, Cadence’s collaboration with Calypto).

    One point you might have overlooked – with the attempted hostile takeover of Mentor by Cadence, could Cadence be contemplating spinning out the C-to-Silicon team (maybe merging with Calypto?) to avoid the regulatory issues they cited (overlap with CatapultC)?

    I think one of the key’s of Cadence’s announcement is the fact that they are the FIRST ESL VENDOR to offer a C-to-GATES solution … everyone else believes C-to-RTL is adequate, and it’s not. Users will not adopt a ESL flow that does not deliver adequate quality of results (QoR) – what sense does it make to increase productivity if product quality declines? That is, who in their right mind would adopt a design flow that produces more gates, consumes more power and offers less performance? I know of none.

    So, QoR is vitally important … and that’s what I believe is the hidden gold nuggest in the Cadence announcement. By embedding RTL Compiler, they can deliver competitive QoR AND eliminate the need for a user to have a Synopsys DC tool/license.

    It’s a very shrewd move by Cadence – kudos to Mac, Steve Carlson and the rest of the crew at Cadence.

    Maybe it also takes a decade to break a market stranglehold like Design Compiler has had … Mentor
    did it to Cadence with Calibre, can Cadence do it to Synopsys with C-to-Silicon?


  4. Grant Martin:

    Dan, thanks for your observations. Your suggestion that Cadence might be contemplating a spinout of the C to Silicon team is of course way beyond anything that I know: intriguing, but I don’t think that would help them with regulatory or antitrust issues. I think spin outs of much larger and longer-lived overlaps, such as the PCB tools or the verification tools, would be required to have a real impact on regulatory issues. Cadence’s current C2S market must be quite small and Mentor’s CatapultC, while sounding reasonably successful in ESL synthesis, is probably not too big in absolute terms (when compared to other slices of EDA).

    Your observation that Cadence’s C2S goes all the way to gates via the embedding of RTL compiler is an interesting one. Cadence implied that for control, this improved results; but I am not sure whether this is really the case for the dataflow applications that many of the other ESL synthesis tools seem to have been concentrating on. But I agree with you that QoR is vital, and it would be fascinating to see comparative benchmarks of different tools running on several applications. Certainly it is good to see the announcement of a development by Cadence in the ESL space (and a development that was telegraphed many years ago and that people have been waiting for).


  5. Michael McNamara:

    Thanks, Grant, Dan, Sean & John for your comments!

    The Cadence C-to-Silicon Compiler uses RTL Compiler to validate that each part of the RTL description CtoS is building will meet the specific area, timing and power goals of the design team, as well as whether the entire circuit will meet the QoR requirements when implemented as gates by RTL Compiler with the chosen technology library and clock speeds. This automated flow enables CtoS to leverage the powerful optimization features of RTL Compiler’s global timing, physical aware synthesis, rather than perhaps fighting with it.

    Customers are free to, and have taken the CtoS generated RTL through other implementation paths; the results are just not as correlated with the model of implementation that CtoS used when it chose the RTL structure and particular sharing and timing relationships. Our RTL works with all flows, but works better with the Encounter RTL Compiler flow.

    As Dan suggests, one gets better results if you can “see over the horizon.” Consider a golfer hitting out of a deep sand trap – some might get lucky and hit the ball into the hole – but most would get better, more consistent results if they could somehow model the entire flight of the ball, including the selection of the putter to be used for the next shot. (So yes, we are taking the fun out of the game of chip design, and making it a boringly predictable enterprise)

  6. Grant Martin:

    Thanks Mac for your response. The linkage of RTL synthesis more tightly into high-level synthesis, that you described is definitely intriguing. Even without comparisons between different competitors tools (something always desired but naturally, vendors are reluctant on this!), it would be interesting to know about the impact of incorporating RTL synthesis into the tool for the purpose of improving QoR, vs. having an unlinked flow. If Cadence had any numbers ref. using RTL compiler in C2S embedded vs. using it “unlinked” (as if it was a 3rd party tool) that would numerically show the advantages of the embedding for different classes of design problems, that would be very interesting to see. Perhaps if the group publishes anything in the future that would be an interesting comparison point.

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