<?xml version="1.0" encoding="UTF-8"?><rss version="2.0"
	xmlns:content="http://purl.org/rss/1.0/modules/content/"
	xmlns:dc="http://purl.org/dc/elements/1.1/"
	xmlns:atom="http://www.w3.org/2005/Atom"
	>
<channel>
	<title>Comments on: Which came first &#8230; the model or the tool?</title>
	<atom:link href="http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/feed/" rel="self" type="application/rss+xml" />
	<link>http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/</link>
	<description>ESL, embedded processors, and more</description>
	<pubDate>Wed, 07 Jan 2009 19:09:41 +0000</pubDate>
	<generator>http://wordpress.org/?v=2.5.1</generator>
		<item>
		<title>By: Jakob Engblom</title>
		<link>http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/#comment-61</link>
		<dc:creator>Jakob Engblom</dc:creator>
		<pubDate>Sun, 08 Jun 2008 14:38:14 +0000</pubDate>
		<guid isPermaLink="false">http://www.chipdesignmag.com/martins/?p=9#comment-61</guid>
		<description>On the other hand, quite often the value of a virtual platform is such that models are developed from the requirement to support software development. So what comes first is the clear need to do software without hardware, and then the models that are needed to fix that get developed. 

Models from the IP vendor are the ideal in many cases, not just for the configurable IP business. But sometimes the IP vendors do not feel like releasing models, or the chips in question are old hat. For example, someone using an oldish Intel chipset along with some standard x86 processor and then a pile of custom ASICs, FPGAs, and standard network controllers to build a board... there is no real "IP" being bought here, really just standard chips. 

What is the model here that makes sense? Right now, it seems to be tool vendors or consultants building these models from the manuals and providing them to the needy software developers. This tends to get resolved simply because the value of doing software development on a model is so great that procuring the models is less of a problem. Just pay someone to do it. And twist some arms to get hte documentation needed.</description>
		<content:encoded><![CDATA[<p>On the other hand, quite often the value of a virtual platform is such that models are developed from the requirement to support software development. So what comes first is the clear need to do software without hardware, and then the models that are needed to fix that get developed. </p>
<p>Models from the IP vendor are the ideal in many cases, not just for the configurable IP business. But sometimes the IP vendors do not feel like releasing models, or the chips in question are old hat. For example, someone using an oldish Intel chipset along with some standard x86 processor and then a pile of custom ASICs, FPGAs, and standard network controllers to build a board&#8230; there is no real &#8220;IP&#8221; being bought here, really just standard chips. </p>
<p>What is the model here that makes sense? Right now, it seems to be tool vendors or consultants building these models from the manuals and providing them to the needy software developers. This tends to get resolved simply because the value of doing software development on a model is so great that procuring the models is less of a problem. Just pay someone to do it. And twist some arms to get hte documentation needed.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Grant Martin</title>
		<link>http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/#comment-48</link>
		<dc:creator>Grant Martin</dc:creator>
		<pubDate>Fri, 30 May 2008 15:01:26 +0000</pubDate>
		<guid isPermaLink="false">http://www.chipdesignmag.com/martins/?p=9#comment-48</guid>
		<description>Gordon, that is a great comment.   With tongue well pressed into my cheek, I would say that the best IP vendors (such as the one I work for) have a strategy whereby models are generated as part of the IP generation process - this is an absolute pre-requisite if you are developing configurable, extensible processor IP, because potential users/customers absolutely need a model base and an ability for automated model re-generation as they iterate over their configurations and extensions.    In many ways the model issue for IP would be resolvablle if all IP vendors took the same tack - that models are an indispensable part of the deliverable, and if they develop their IP and models in parallel with a configurable idea in mind, the users/architects would be much better off.</description>
		<content:encoded><![CDATA[<p>Gordon, that is a great comment.   With tongue well pressed into my cheek, I would say that the best IP vendors (such as the one I work for) have a strategy whereby models are generated as part of the IP generation process - this is an absolute pre-requisite if you are developing configurable, extensible processor IP, because potential users/customers absolutely need a model base and an ability for automated model re-generation as they iterate over their configurations and extensions.    In many ways the model issue for IP would be resolvablle if all IP vendors took the same tack - that models are an indispensable part of the deliverable, and if they develop their IP and models in parallel with a configurable idea in mind, the users/architects would be much better off.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Gordon McGregor</title>
		<link>http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/#comment-47</link>
		<dc:creator>Gordon McGregor</dc:creator>
		<pubDate>Fri, 30 May 2008 04:30:37 +0000</pubDate>
		<guid isPermaLink="false">http://www.chipdesignmag.com/martins/?p=9#comment-47</guid>
		<description>Model availability always gates the use of any sort of modeling tool. I've found it more pressing in the system architecture space than say for software development, simply because system architecture is the bit you come to first, when you start thinking about building a platform/chip/ HW/SW widget.

Marketing comes up with a grand idea. Then if you are into the whole ESL thing, you almost immediately want to start slinging prototypes around, exploring the performance, maybe running snippets of algorithms, exploring the bandwidth issues and other performance corners that are the focus of much of the back and forth of the initial system and architectural design.

Peripherals on the boundaries of the chip functionality can be happily abstracted away to a large degree, but models of those core bits that really influence the performance are key. Worse still when you are considering evaluating different options from external IP vendors.

The models are never ready when you want them, usually because the companies are still designing the IP and either do their design first and create a model last, or wrote the model in some other language than the one you want to use, for a customer that uses a different interface or hooks up to a different sort of modeling tool.

All of these are very solvable problems and can easily be worked around with a 6 month lead time and some money and engineers thrown at the problem. 

But for system design, you need those models now and you'd better be finished in 6 months time or maybe turning it into a nearly final virtual prototype to be starting your software development.

The killer for ESL IP availability, if you want to be using anywhere near current IP or the latest and greatest processors is the complete lack of lead time on the need for models. Excel almost always wins that race.</description>
		<content:encoded><![CDATA[<p>Model availability always gates the use of any sort of modeling tool. I&#8217;ve found it more pressing in the system architecture space than say for software development, simply because system architecture is the bit you come to first, when you start thinking about building a platform/chip/ HW/SW widget.</p>
<p>Marketing comes up with a grand idea. Then if you are into the whole ESL thing, you almost immediately want to start slinging prototypes around, exploring the performance, maybe running snippets of algorithms, exploring the bandwidth issues and other performance corners that are the focus of much of the back and forth of the initial system and architectural design.</p>
<p>Peripherals on the boundaries of the chip functionality can be happily abstracted away to a large degree, but models of those core bits that really influence the performance are key. Worse still when you are considering evaluating different options from external IP vendors.</p>
<p>The models are never ready when you want them, usually because the companies are still designing the IP and either do their design first and create a model last, or wrote the model in some other language than the one you want to use, for a customer that uses a different interface or hooks up to a different sort of modeling tool.</p>
<p>All of these are very solvable problems and can easily be worked around with a 6 month lead time and some money and engineers thrown at the problem. </p>
<p>But for system design, you need those models now and you&#8217;d better be finished in 6 months time or maybe turning it into a nearly final virtual prototype to be starting your software development.</p>
<p>The killer for ESL IP availability, if you want to be using anywhere near current IP or the latest and greatest processors is the complete lack of lead time on the need for models. Excel almost always wins that race.</p>
]]></content:encoded>
	</item>
	<item>
		<title>By: Adam Donlin</title>
		<link>http://www.chipdesignmag.com/martins/2008/05/19/which-came-first-the-model-or-the-tool/#comment-40</link>
		<dc:creator>Adam Donlin</dc:creator>
		<pubDate>Fri, 23 May 2008 05:15:03 +0000</pubDate>
		<guid isPermaLink="false">http://www.chipdesignmag.com/martins/?p=9#comment-40</guid>
		<description>I would suggest that models drive the adoption of ESL for software development and architecture analysis.    It is very difficult to take advantage of ESL techniques if you're missing one or more important component models.     Tools, on the other hand, usually don't have all the features required or desired so users improvise.   An example of this would be "POSC" (the OSCI kernel) is spartan but popular.  It is unconstrained and relatively easy to augment.

Do tools make it easier to write and use models?   I would suggest that tools can add to the cost of developing models because many of the value add features require the model developer learn and use proprietary APIs.   This is a significant burden when the model is to be reused in several different tools.    In ESL, interoperability extends far beyond the transaction interfaces.   We still must take huge strides in interoperability for model configuration, instrumentation and debug.</description>
		<content:encoded><![CDATA[<p>I would suggest that models drive the adoption of ESL for software development and architecture analysis.    It is very difficult to take advantage of ESL techniques if you&#8217;re missing one or more important component models.     Tools, on the other hand, usually don&#8217;t have all the features required or desired so users improvise.   An example of this would be &#8220;POSC&#8221; (the OSCI kernel) is spartan but popular.  It is unconstrained and relatively easy to augment.</p>
<p>Do tools make it easier to write and use models?   I would suggest that tools can add to the cost of developing models because many of the value add features require the model developer learn and use proprietary APIs.   This is a significant burden when the model is to be reused in several different tools.    In ESL, interoperability extends far beyond the transaction interfaces.   We still must take huge strides in interoperability for model configuration, instrumentation and debug.</p>
]]></content:encoded>
	</item>
</channel>
</rss>
