Taken for Granted

The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12.

DATE has always been a favourite conference of mine to attend, with its excellent technical programme from its beginnings in the late 1990s, and its focus on system level and systems design (not to say that it does not cover other aspects of EDA, but ESL has been a strong focus from the beginnings).

I am unlikely to be able to attend DATE 2010 in person this year, but was on the programme committee, as a co-chair for the System Specification and Modelling topic, together with my good friend Eugenio Villar of the University of Cantabria, Spain.  I also helped organise a couple of panels:  6.8 – The Challenges of Heterogeneous Multi-core Debug, and 7.8 – Who is Closing the Embedded Software Design Gap?, (organised together with Wolfgang Ecker of Infineon, who will moderate it).   The panel on heterogeneous multi-core debug features several designers from the Dresden area as well as Stephen Lauterbach of Lauterbach.     The panel on embedded software has participants from Germany, France and the U.S.

My colleague Chris Rowen (Founder and CTO of Tensilica, where I work), is due to give a talk on the topic “FABULOUS, FRIGHTENING AND TRUE:  STORIES OF MULTICORE SOC DESIGN FOR WIRELESS BASEBAND” in session 7.1 on Wednesday afternoon March 10.  He is also participating in panel 2.8, “Are we there yet? Has System Assembly from IP Blocks Become Like Connecting LEGO Blocks?” on Tuesday and moderating panel 10.8, “Embedded Software Testing: What Kind of Problem is This?” on Thursday.

The other thing that would be nice to be at DATE 2010 for would be to hang about the Springer booth which should be selling (and I hope selling out) the new book by Brian Bailey and myself, “ESL Models and their Application:  Electronic System Level Design and Verification in Practice“.   If you are there and buy it, I hope you find it useful (of course, you can buy it online at the Springer site and at places like Amazon).

But beyond my own concerns, DATE has many interesting things to offer attendees.  Other technical sessions that look interesting to me are:

• Keynotes by Alberto Sangiovanni-Vincentelli and Herman Eul
• Session 3.4, “Application Development for Multicores”
• Session 8.3, “System Modelling for Design Space Exploration and Validation”
• Session 9.3, “Language Based Approaches to System Level Design”
• Session 10.4, “Architectures for Next Generation Wireless Communication”

But check out the programme for yourself – there is lots of interest.  With tutorials on Monday and workshops on Friday, you could spend a technically rewarding and very busy week in Dresden.

If you manage to get to DATE I hope you can leave a comment about it here.  I’ll be interested in hearing how it goes.

Although I am probably not going to  be able to attend, you might want to check out this year’s Electronic Design Process Symposium whose web page is here.

Zoe Paul, The Amazons I

The symposium is held at the Monterey Beach Hotel in Monterey, California – a pretty interesting location – and this year will be April 8-9.  When I have attended, the size ranged from about 25 to 50 people, which allowed good discussions of some of the interesting trends and changes in electronic design and methodology.

This years draft advance programme includes a number of interesting topics and speakers including parallelism for EDA, high level design and ESL, and power, and there is no doubt room for more ideas.

It is also not too late (not by a long shot) to submit a proposal for a paper yourself – the submission deadline is February 26.   Based on my experiences there, you could have an interesting time.

Early registration deadline is March 1, which also gives you a good month to think about it.

Last year I worked with Brian Bailey and a number of other contributors on a new book on ESL, just published by Springer.

“ESL Models and their Application:  Electronic System Design and Verification in Practice” is a complement to our earlier book (with Andrew Piziali and a number of contributors) “ESL Design and Verification:  A prescription for electronic system level methodology” (Elsevier Morgan Kaufmann, 2007).

The new book concentrates on giving a snapshot of actual ESL practice in 2009-2010, illustrating the various kinds of models and ESL applications in widespread use today, with worked out examples illustrating use of some of today’s key technologies.  The examples are all based on real tool use, using particular tools for each example (although others could have been used instead).

Springer should be selling this at upcoming conferences such as DATE 2010 and DAC 2010, so please check it out if you are there.   You can also find it on Amazon here.

If you have a comment on the book – good or bad – please post it here!  Your feedback is always welcome.

Today (Monday November 2, 2009) I attended a special session held alongside ICCAD 2009 at the Doubletree Hotel. Paul McLellan and Jim Hogan presented some ideas on What EDA needs to change for 2020 success to a group of 25-30 people including several who blog on EDA related topics. There was a bit of discussion of the ideas presented although only a few of the attendees made comments, which was a shame.   Paul and Jim’s presentations are here, courtesy of Si2.

The biggest idea, agree on both by Paul and Jim, was that design is going to change to a “Software Signoff”, reminiscent of the earlier change to an “RTL signoff”, and that EDA is going to have to follow this change to survive. The role of FPGA in design and the growth of complex processor-centric FPGA design were also highlighted, although I asked whether there was real data that as ASICs and ASSPs decline in numbers and complex FPGAs rise, are the EDA dollars/yen/yuan/Euros following the shift? Unfortunately, there still seems to be a lack of hard data here and thus this still comes across as a prediction of change more than a revealed change.

The other thing I noticed is that most of the questions and comments, and diversions, seemed to come from people with a hardware-EDA focus, not a software focus at all (with perhaps my friend Frank Schirrmeister being an exception, and maybe myself, although I live in both worlds at once). This makes me wonder if EDA will just wither away into a small core group of tools used for the hardware design flow and linked closely to the fabs that remain, and that the new design tools of the future will come from a very different source. Certainly a hardware-focused EDA industry does not “get” software, which was commented on at the forum – and companies like VaST, for example, don’t participate in EDA related events because it does not seem relevant to their users.

Perhaps an ICCAD is just not the right forum for such a discussion because of its hard-core EDA/hardware focus. Although I later helped do an embedded tutorial on Embedded Processors, Methods and Applications: Computer Architects Perspective, with Sri Parameswaran and Anand Raghunathan that drew about 40 people to hear about primarily SW and architecture-centred topics – which was welcome.

As I have said before, I’m no Nostradamus, and predicting the future is beyond my ken, but something has to change in EDA, as the two speakers concluded. What will that be?

I have been remiss in writing anything on this blog for the past month. While I am certainly not Too Big to Fail (although I have found all my failures to be good lessons for the future) and could certainly be called Too Big, the last couple of months have definitely left me Too Busy to Fulminate.

Among other things, I am proofing my next book (co-written with Brian Bailey) that we hope will be out early in the new year from Springer: ESL Models and their Application: Electronic System Level Design and Verification in Practice. Of course, I think it will be a good one!

But I do hope to be fulminating again soon! Watch this space.

I was a participant yesterday (Wednesday September 16) in a panel at the EETimes SoC Virtual Conference, on the Economics of Next-Generation SoC Design: A node too far?. This was an interesting comparison point to the first online conference I was part of in 2002, the SoC Online conference. The technology worked better (as one would hope after 7 years!) although it appears not perfectly for all attendees, as Lou Covey writes. I have been extremely busy of late and could not attend all the sessions that I wanted to, although I listened in to most of the keynotes by Rajeev Madhavan and Gerry Gaffney.

The panel discussion was well organised, well moderated by Dylan McGrath and it was a pleasure to participate along with Sven Andersson of Realtime Embedded AB, Ron Collett of Numetrics and Steve Douglass of Xilinx. Monitoring the attendees, I noticed a peak attendance of about 130 (not bad considering this was from 5-6 Eastern Time, 2-3 Pacific Time, and the last session of the virtual conference). There were also 5-6 user questions and some good discussion.

I think the format is an interesting one to keep experimenting with, as I noted after watching the EETImes Virtual Conference on Multicore in June. The parts that work best are keynotes and talks which are essentially webinars, which work pretty well; and the panel format which uses the same technology to push slides and audio and get audience questions. We’ll have to see what the eventual role of these virtual events settles down to be. Unlike Lou Covey, and some of the people he was virtually chatting to, I have found value in webinars – although I try to be pretty selective.

DAC 2009 is truly well and over, but it is still a topic of interest. Sean Murphy has a page pointing to a host of blog posts about it – before, during and after – that is an excellent resource. There continues to be an active discussion of the announced attendance numbers, and what they mean (see, for example, Kevin Morris, Paul Mclellan and Lou Covey). I’ve come up with my own thoughts, in no particular order, that might lead to improvements in the conference:

1. First, I think it is time for DAC to become very transparent about its attendance numbers, both current and historical. I cannot find any place on the DAC web site that lists the historical and current attendance numbers (broken into the various categories – e.g. exhibit only, full conference, exhibitor staff and “other”; and both preliminary and final figures). The preliminary figures are press-released for the current year but have to be retrieved from PR archive sites or other miscellaneous places on the web if you want to find past years. The definitions of preliminary (e.g., pre-registered) vs. final (I assume this is pre-registered people who showed up plus walk-in registrations) are not clear. And the final numbers are extremely hard – almost impossible – to find on the web. Since people are interested in attendance numbers as an indicator of the health of the EDA industry, the conference and maybe even of electronic design, and since they should not be secret, I don’t know why DAC shouldn’t be quite transparent about these numbers and post them prominently on their web site. In the absence of the facts, people will speculate or analyse based on whatever bits of information they have.
2. The future of DAC lies in attracting a wider design community and in my opinion becoming as much or more about design as about automation. That is, the emphasis of DAC should continue a shift from a focus in the technical programme on EDA algorithms and research and move quickly to a focus on design methods, design issues, designer problems and designer experiences. And this should bring with it a stronger focus on applications. The user track DAC instituted this year is an important step in that direction. But it was a bit of a sideshow and occupied only one out of seven parallel technical conference tracks. The focus should immediately and radically shift so that half of DAC’s conference programme is designer, application and user experience and half being the more traditional EDA algorithm work. This is nothing more than returning DAC more to its roots as being grounded in and reporting on real design experience.
3. To do this, the programme committee needs to be reworked so that a majority of the members are from industry (or the academic research programme committee part should be shrunk so that the user track committee is larger than it). This is a lot of work and a hard slog. It would be impossible to do this in one year. My experience as co-chair of the programme committee in 2005 and 2006 (for design methods) indicated to me that it takes a huge amount of effort and a lot of persuasion to sign up each new industrial or designer member. But the goal is worthwhile.
4. If DAC really does re-focus so that real design becomes its major focus, it is clear, as many have commented, that it needs to embrace the wider topics of design including FPGAs, embedded software, and board design, as well as the IC design that it has focused on in the technical conference and exhibit in recent years. Again, this is nothing more than a return to its roots. But to do this well it needs a lot of information about what the real worldwide design community does and what it wants in a technical conference with an exhibition. Since the current EDA vendor community seems to focus mostly on the IC design community, the conference needs a lot of information about all these other aspects of design.
5. Rome was not built in one day, as John Heywood said in 1546! . But a radical transition can’t take many years either. This year I think we reached the end of ESL existentialism (the constant questioning about whether ESL exists) because I think a number of people now recognise that it is real. With a transformation in DAC to serve the really wide worldwide electronic-based product design community (of course including embedded software), we might someday see an end to the perennial questioning: is EDA dying? and is DAC dying (or not relevant). It would be nice to see debates on different topics emerge!
6. Finally, with a focus on design and applications, how about a new name? DAC is too established an acronym to tamper with – but how about it meaning “Design and Application Conference” rather than “Design Automation Conference”?

I would welcome your comments and thoughts on these suggestions and on DAC …..

I had the great privilege on Friday evening of attending an informal reception hosted by Alain Labat, CEO of VaST, in honour of Alberto Sangiovanni-Vincentelli and his recent receipt of the 2009 IEEE/Royal Society of Edinburgh Wolfson James Clerk Maxwell award.

Alberto Sangiovanni-Vincentelli

During the reception I recalled that I first met Alberto 17 years ago, when a group of us from Nortel in Ottawa visited Cadence in San Jose to talk about partnership.   Since then I have had the opportunity to work with him on and off on a number of things, especially while I was at Cadence.

The reception was attended by several of Alberto’s former students, now spread around many places, and colleagues from various times over the past many years.    Alberto said very generous words about all the students and colleagues who were there.  It was a very nice event, and many thanks to Alain Labat for hosting it, and of course, congratulations to Alberto for his recent award and his long, influential, and continuing career.

This is the last post I will write based on DAC 2009 (unless, of course, something occurs to me next week!). This one is sparked by several remarks made in a number of the presentations I attended at DAC, to do with the relationship between Platform-Based Design (PBD) and Virtual Platforms or Virtual Prototypes (VP). It seems, as we predicted more than a decade ago in Surviving the SoC Revolution: a guide to platform-based design, that there is a mutually beneficial and symbiotic relationship between the notion of a system or SoC “platform”, and the high-level system models or “virtual platforms” that assist in designing and verifying at the ESL level. At the DAC 2009 Virtual Platform Workshop, Ramesh Chandra of Qualcomm was very explicit on this theme, and that the platform-based methodology, based on virtual platforms, was the way to go from architectural development to microarchitectural and more detailed design development.

Since the concepts of platform based design are now well established for complex SoC design, and since virtual platforms/high level system modelling is a reality of what we call “ESL” (along with high-level synthesis), we can expect to see further consolidation of design practices along these lines in the next few years. This still leaves many interesting system level design problems to solve – among which are to build solid flows between algorithm development and architectural specification and development – which are still at a pretty rudimentary stage, although there is a lot of interesting research and some early ideas being worked. The application-specific instruction set processor (ASIP) idea is one that allows interesting links between algorithms and optimal implementations to be worked out, of course!

DAC 2009 announced its preliminary attendance numbers on Wednesday July 29.  Here they are:

• Exhibit only – 3247
• Technical conference – 1888
• Total – 5135

(I don’t believe this includes exhibit booth staff, etc.).

How does this compare with previous years?  We need to take the preliminary attendance numbers announced for each year to be comparable (these are based on pre-registrations; later the adjusted attendance numbers are announced).  So here we go:

• 2008 – Anaheim – Exhibit only 2405; conference 2423; total 4828
• 2007 – San Diego – total announced as 5100
• 2006 – San Francisco – Exhibit 3421; conference 3231; total 6652

Since these are preliminary numbers for each year, a better comparison will come with the final numbers next month.   Exhibit attendance increased from 2008 significantly, no doubt helped by being in San Francisco (see 2006 – reasonably comparable) – and the return of Free Monday also no doubt helped.   Conference attendance seems to be declining.   One recommendation I would make to DAC,  based on my limited attendance at the User Track yesterday (which I thought quite good), would be to try to increase the user track and the relevance of the conference part to working engineers and designers.   This year was a good start, but it certainly will require continued development effort to keep improving.