Taken for Granted

On Thursday June 17, DAC had a special set of sessions labelled “Embedded/SOC Enablement Day”, with talks from a variety of people from a variety of companies talking about their strategies and tradeoff choices for complex SOCs, usually in embedded systems. This included a keynote by Gadi Singer of Intel. As I reported in my note on Tuesday, the “P-word” (Platform, and Platform-based-design) have returned with a vengeance.  This was noticeable in the talks by Gadi Singer (Intel), Yervant Zorian (Virage Logic), John Bruggeman (Cadence – and a passionate speaker about EDA 360 – this was the first time I had seen him talk), Ivo Bolsens (Xilinx), Shauh-Teh Juang (TSMC)  and Rob Aitken (ARM).   Ten Years After (well, maybe eleven or twelve) and the design approach we observed, and predicted would become ubiquitous, has indeed become accepted and ubiquitous.

Later that day I attended the Panel Discussion on “What Input Language is the best choice for High-Level Synthesis (HLS)?”   No real surprises here, with 5 of 6 panelists being from the C/C++/SystemC camp and one being from Bluespec (Rishiyur Nikhil), that C and its variants was the preference advocated by the majority of the panelists.  Dan Gajski of UC Irvine had tried with some pre-questioning of the panelists and summarising their responses along various lines, to get some reasons for their preferences (features and capabilities).   As someone a little biased to C/C++ with selective use of SystemC where necessary to express some communications aspects of systems, the idea of teaching designers a new language, as with Bluespec (perhaps better described as a new semantic expressed in extensions to SystemVerilog) is less appealing from a practical point of view.  Although, looking at reference code, as I asked the panelists, one wonders about the level of teaching required for the “older” languages, as much of it can be very poorly written.   It seems inevitable that C/C++/SystemC and combinations thereof will continue to be the mainstream input form for the considerable future.

On the last day of DAC (Friday), I was part of a tutorial on “SystemC for Holistic System Design with Digital Hardware, Analog Hardware, and Software”, talking about Application-Specific Instruction set Processor design (ASIPs) using Tensilica as an example, hardware-software tradeoffs in this style of design, and how via SystemC-based system models, it fits into modelling higher level heterogeneous systems.   My fellow tutorial instructors talked about analogue and mixed-signal design and verification using system-level modelling approaches.   It seemed a fitting end to what overall I think must be judged a successful DAC and one that reflected some recovery in the electronic design industry.   I see DAC has released their preliminary attendance figures which seemed a little up on last year, at least in several categories.

On Wednesday June 16 I moderated a special session at DAC 2010 in the morning: “A Decade of NOC Research – Where Do We Stand?”.  This was an extremely interesting special session, organised by Anand Ragunathan and Sri Parameswaran, with three excellent speakers:

1. Giovanni De Micheli of EPF Lausanne, Switzerland, who gave an overview of NOCs (Networks on Chips):  “Networks on Chips:  From Research to Products.
2. Kees Goossens of TU Eindhoven, the Netherlands, who talked more deeply on “The Aethereal Network-on-Chip after Ten Years:  Goals, Evolution, Lessons, and Future”
3. Bruce Mathewson, AMBA architect and Fellow at ARM in Cambridge, UK:  “The Evolution of SOC Interconnect and How NOC Fits Within it”.

Each talk was highly informative and entertaining, and the sum of the three gave a really good view of NOC past present and future.  The up to 90 people in the room seemed to agree.   Each talk had questions, and then we concluded the two hour session with a panel discussion of 30 minutes on relevant NOC questions.   The audience provided every question (I took the opportunity to lob in one of my own, but it was not necessary) and there was an excellent debate on NOC.

Kaist NOC research chip, Korea

One issue that came to the fore in the talks and panel discussion is that the definition of NOC is extremely elastic.   It can be defined by characteristics, but many of the attributes of a NOC have been influential in advanced hierarchical bus style interconnect such as the relatively recent AMBA4 by ARM.   As a result, I would suggest it is time to think of retiring the NOC term and use “advanced interconnect” instead.   Future complex SOCs will use interconnect that incorporates attributes and concepts drawn from buses, point to point interconnect and NOCs and may have several different styles used in different subsystems,  with a chip-level interconnect concept suitable to the application.   Thus perhaps without having very many commercial examples of chips that are “pure NOCs”, we can declare victory, retire the term, and move onto the more important issues of specifying, designing and verifying the complex interconnect schemes that future designs will need.

A second interesting issue is the growing importance of tools for designing advanced interconnect for SOC, whether bus or NOC based or mixtures of all types.   In the past design groups could muddle through evolving from legacy buses, but this looks less likely in the future and NOCs in particular need modeling and analysis tools to make sure they are right for the application, and implemented with the right characteristics.  The EDA industry in particular seems to be letting the side down here, as the panelists and audience did not see EDA/ESL vendors offering anything much in this domain.   At a crucial time for the EDA industry and with major changes afoot, highlighting this future opportunity at DAC sounds like the right thing to do.

My thanks again to the organisers and speakers.  It was a great session of high value to all who attended.   I was glad that I was asked to help out.

During today at DAC 2010 I was able to attend some of management day, which I had not attended before. I saw a very interesting presentation by Ken Wagner of PMC-Sierra called “The case for platform devices” which outlined PMC’s design methodology for chip platforms as a vehicle for delivering functionality to users. His definition included the well-formed phrase: “having only a fraction of its features active in any single customer application”. In PMC, this extends to actually having different bonded-out devices using the same core chip, with different datasheets and thus different instantiations or derivatives from the common platform.
He also said they sometimes do a “pseudo-ASIC” based on a platform device with some special design for a single customer. PMC-Sierra builds a business case for doing platform devices vs. ASICs, and count on a 2-3 year design cycle, allowing for feature change during the development, while guarding against constant churn.
PMC also counts for 1 spin of a platform device and don’t plan for a test chip. High mixed-signal content makes their designs more challenging than a pure digital circuit, and other lessons learned include the benefits of virtual platform models to deal with SW and system complexity, and the need for sophisticated power control mechanisms.
The theme was briefly reiterated in a later management day talk by Karim Arabi of Qualcomm when he also mentioned platform-based design as part of their strategy.

One reason I found this so interesting is that it is now 11 years since I co-wrote, with several colleagues from Cadence, “Surviving the SOC Revolution: A guide to platform-based design”. And our work started more than 12 years ago. The intervening more than a decade has seen the use of platforms for complex SOCs increase continually.

Interestingly, with EDA360, Cadence seems to have rediscovered platforms without any historical memory of what we did more than 10 years ago. Such is the lack of history in EDA and electronics! To quote:

“What they are demanding, in effect, are application-ready platforms with hardware and software for a given application, such as mobile computing. The completeness and relevance of an application-ready platform has become as important as having the latest, greatest, most power-efficient silicon. The newcomers differentiate their products by building unique software applications on top of those platforms.”

This could have been written 11 years ago.  In fact, it was and we did, albeit using somewhat different words. There are several relevant quotes I could use here, including one about prophets being without honour in their hometown, but I guess there is no need to dwell on it.

DAC 2010 opened with the Monday Exhibits day. I showed up at the DAC Pavilion to hear Gary Smith’s “What to see at DAC” only to be regaled by music  Lousiana style, what I would call Semi-Zydeco (not Semiconductors) with Gary on  washboard and vocals, Mike Santarini on guitar, Bob Gardner on what I think was a sax (alto or soprano? I  could be quite wrong) and tambourine, and Peggy Aycinena on accordion. The crowd was suitably entertained, although a nearby comment was that Gary should keep his day job, and I did think he may not be auditioning for American Idol next year. He could be known as the William Hung of EDA, but he sounded a lot better than I do in the shower,  I am sure.

Gary followed by what to see at DAC, which didn’t contain too many surprises. He then did a repeat of his talk of the previous evening which I skipped out on.  The pavilion was quite packed out and the  crowds on the exhibit floor seemed good, although I am a pretty poor judge of crowd size normally.

After an hour on the floor I went back to the Pavilion to watch the panel “The Multiplier Effect: Developing Multicore, Multi-OS Applications”. However, it could have been called “The Substitutes”, because Paul Dempsey was supposed to moderate, replaced by Steve Leibson, my friend and colleague now at Denali (i.e. Cadence), Daniel Forsgren of Enea was replaced by Christopher (I am afraid I did not write down the last name) from Enea, Simon Milner of Marvell was played by the real Simon Milner of Marvell, and I was a last minute draft pick substitute for Alan Gatherer of Huawei. Poor substitute I may have been, but the subject was multicore and I could probably talk about that in my sleep – and maybe was dreaming! In any case I held my own and I hope said something someone in the audience found useful.

The only thing I can say about it was – be careful where you show up, you may become part of the show. But be brave and always try to help out if you can.

Tonight are a reception and the Denali party. Better hands than mine will no doubt talk about the Denali party when it is all over.

Leonard Cohen, 1956

The title of course being drawn from Leonard Cohen’s first book of poetry, published only 2 years after I was born!

Looking back at my posts from DAC 2009, there was a considerable similarity between Day 0 then and Day 0 yesterday.   First was the CODES+ISSS 2010 programme committee meeting (part of ESWeek 2010 in October in Arizona), a solid morning of work, again with my appreciation of the excellent and thorough volunteer work done by the mostly academic programme committees of conferences.       Despite a drop of in submissions, the quality of ESWeek 2010 will no doubt be high.

Then the NASCUG 2010 DAC meeting, with some presentations by users and suppliers of tools on what they are doing with SystemC.  No particularly startling revelations or new use models – about 55 people in the room and a smattering of questions.  SystemC, after almost a decade, is part of the furniture of EDA and ESL just like Verilog and other languages.   It’s something you expect to see in the room, rather than something unusual and new.   Eventually the presentations will I am sure be posted at the NASCUG site, and video too (it was being videoed).

Following was the DAC welcome reception, which filled a room with several hundred people, a free bar, and a tremendous amount of noise.   The conference chair and sponsors could not be heard when they made their opening remarks, but it was a nice chance to meet old colleagues.  This made it a wise decision to separate the now rather traditional Gary Smith overview talk into a separate room, because the hard core who moved from the reception to Gary’s room were there to hear him rather than gossip at the back and drown out the proceedings.

Mary Olsson of GarySmith EDA first talked about the 3D and TSV (Through Silicon Vias”) technologies that she saw emerging and moving from the fringe more into the mainstream of implementation over the next few years.  Calling future trends is always a dangerous business and it will be interesting to observe whether this really becomes the mainstream, but there does seem to be considerable interest in these technologies along with backing from all the parties.

This was followed by Gary Smith talking about Design costs of EDA.   Richard Goering already did a writeup about this.  From my perspective, I am not sure about Gary’s categories of EDA users into Power Users and Upper Mainstream etc.    The power to name things – to name categories and create taxonomies – is an important one.   I guess if you use these as shorthand for methodologies, so that a design team might end up using a “Power methodology” for an advanced design pushing at the fringes, and another design team at the same company might use an “Upper Mainstream” methodology for a more conventional design, then it might fit.

Again Gary talked about ESL adoption and SW tools as the most important trends and the way to control design costs based on the ITRS cost model which he is the main driver for.   But the time frames seem very dragged out and similar to previous predictions, just moved to the right.   I am not sure we will really wait for the year 2025 (!   I will be 70!) for the “executable specification”!   I don’t think methodologies move in predictable 2 year time slices.  When they shift, I think it is more tectonic than that – the whole plate moves fairly rapidly.   Perhaps like the evolutionary bursts of rapid change that Steven Jay Gould called “punctuated equilibrium“?

Lots more to do at DAC 2010 and I am looking forward to the rest of it.

I arrived at Oakland Airport to fly to the triply-named Orange County/Santa Ana/John Wayne airport to attend DAC starting tomorrow (programme committee meeting for CODES+ISSS 2010, plus some of the opening receptions tomorrow evening) only to find that my Southwest flight was delayed 2 hours (so was the follow on, but the previous one left on time, as Murphy would have predicted). However, that gave me time to watch the end of the England-US first round World Cup match, which ended in a 1-1 draw. Combined with the South Africa-Mexico 1-1 draw, in some ways it is an auspicious start to the World Cup, where my youngest daughter says that rather than choose a favourite team to root for, she “just hopes that everyone has a good time playing”. Our household is a complicated one since we all have triple Canadian-British-American citizenship, although if Canada had qualified I have no doubt who most of us would have been rooting for!

Despite the delay in getting there, it does give me time to try Oakland Airport’s free wifi service, which allowed me to post this for free. And to read a bit of Paul Mclellan’s EDA Graffiti book that I posted about. It’s good for grazing, consisting of many short segments amplified from his blog. I must say, to quote Justice Oliphant , it is full of “good old Northern Common Sense” (now there’s a reference for you to puzzle out!).

I’m looking forward to DAC for a catch up especially on advanced design methods being used by design teams, the latest in ESL, and I hope a chance to meet some old friends and colleagues for a good gossip.  With all the recent EDA industry announcements including Cadence buying Denali, and Synopsys buying Virage and picking up the Synfora technology, there is a lot to gossip about.

Yesterday an old friend and colleague Paul McLellan dropped by with a couple of copies of his new book EDAgraffiti, which he wrote based on his well-known blog hosted by EDN magazine, amplifying and expanding on many of the themes he has written about. I hope to read it and consider doing a review of it in IEEE Design and Test - it would certainly be a different kind of book to review than the normal technical round. You can read more about it in Paul’s blog and also buy it at CreateSpace here.

Paul McLellan

Equally interesting to the book itself is the way it was written and published. Paul decided to self-publish using the CreateSpace service, which allows an extremely attractive price ($25 US plus shipping) and a much higher royalty to the author. Having co-written or co-edited ten books myself, plus contributed chapters to many others, the self-publishing trend is one that has interested me for a while. At one point several colleagues and I were thinking of doing a self-published book but the project was suspended for lack of time. Initially I was the most skeptical but it still sounds like something worth trying to do. Paul said the process was relatively painless. It will be interesting to see how well his book does vs. the more traditional publishing and sales route, especially when he decides to make it available electronically.

The world is changing, often faster than we would like, but it keeps life interesting!

It’s May, and an old man’s thoughts turn to DAC in June: June 13-18 in Anaheim. This years Design Automation Conference looks like a bit of a year of changes. I will write later about some interesting events during the conference, but this note is entirely social.

As many of you may know, Denali is a strong DAC supporter and of course everyone hopes they will bring that spirit into Cadence since they were just bought by Cadence. In 2010, they are sponsoring the DAC party which has been moved to Tuesday June 15 from its traditional Wednesday night. But Denali is also continuing their own party, which is now on Monday June 14 at the House of Blues in one of the Disney areas near the convention centre and hotels (actually, a pleasant evening stroll). This needs special signup at the Denali web pages here. You need to sign up on their web page now and pick up a ticket on Monday June 14 at their booth on the exhibit floor during exhibit hours.

Denali party DAC 2009

Denali was also a co-sponsor of a Free Exhibit Pass promotion for DAC along with Atrenta and Springsoft.

I think this very strong support for DAC is very commendable. I will be attending DAC all week and hope to see you there at both parties, as well as in the conference and the exhibit. I will write another note with my plans on the technical side. But let’s not forget the social side of our business and I hope for all of you, passion.

It has now been more than a week – time for the dust to settle a little bit, on the news from two weeks ago and last week that Synopsys had acquired VaST, and then CoWare; and that Intel had acquired Virtutech and was planning to merge it into its Wind River subsidiary.

Several commentators have talked about these acquisitions, including:

1. Paul Mclellan on VaST, Virtutech and CoWare
2. Brian Bailey on VaST, Virtutech, CoWare, and additional comments  here.
3. Gabe Moretti on VaST and more generally on Synopsys and virtual prototyping.
4. Clive Maxfield here.

The books ESL Design and Verification:  a prescription for electronic  system-level methodology, and ESL Models and their Application: Electronic System Level Design and Verification in Practice, which I co-wrote, both deal with virtual platforms and prototyping in some detail.

Bill Murray in SCDSource had a couple of excellent writeups on virtual prototypes in late 2007 and early 2008:  Virtual Platforms – a reality check, Part 1 and Part 2.

It’s of course too early to know what the specific plans Synopsys and Intel (Wind River) have for the technology they have acquired and the people working on it.  But there are a couple of comments worth making here:

1. the three V’s of virtual prototyping – Virtio, VaST, and Virtutech – are gone or will be going.   For fans of alliteration, this is a great shame.
2. More important is to speculate on what the companies might do with the technology in this domain in the future.   As discussed in the two books I reference above, there are many use models for system models and virtual platforms.   Some of these are offered by the commercial tools, or at least some of them.   Some tools offer only instruction-accurate (fast functional) system modelling; others offer both that and cycle-accurate system and component models.  Both levels have their uses and the modelling approaches also vary.   Will consolidation lead to more complete sets of model offerings?
3. In addition, one big gap that I see in virtual prototyping is to bring it together with particular software development methodologies and tools to give users a faster and better way to carry out multicore partitioning onto heterogeneous or homogeneous clusters of processors, and thus move more rapidly to a partitioned system architecture.   The virtual prototypes allow you to simulate the results of decisions but partitioning software onto multiple processors, setting up communications libraries and methods between them, and modifying the software to accommodate different mappings, is still a fairly tedious manual process.   Might the consolidated resources of some of these companies allow them to make advances in this area?

As always, I welcome your comments.

The Design Automation and Test in Europe 2010 conference will be held in Dresden Germany from March 8 to 12.

DATE has always been a favourite conference of mine to attend, with its excellent technical programme from its beginnings in the late 1990s, and its focus on system level and systems design (not to say that it does not cover other aspects of EDA, but ESL has been a strong focus from the beginnings).

I am unlikely to be able to attend DATE 2010 in person this year, but was on the programme committee, as a co-chair for the System Specification and Modelling topic, together with my good friend Eugenio Villar of the University of Cantabria, Spain.  I also helped organise a couple of panels:  6.8 – The Challenges of Heterogeneous Multi-core Debug, and 7.8 – Who is Closing the Embedded Software Design Gap?, (organised together with Wolfgang Ecker of Infineon, who will moderate it).   The panel on heterogeneous multi-core debug features several designers from the Dresden area as well as Stephen Lauterbach of Lauterbach.     The panel on embedded software has participants from Germany, France and the U.S.

My colleague Chris Rowen (Founder and CTO of Tensilica, where I work), is due to give a talk on the topic “FABULOUS, FRIGHTENING AND TRUE:  STORIES OF MULTICORE SOC DESIGN FOR WIRELESS BASEBAND” in session 7.1 on Wednesday afternoon March 10.  He is also participating in panel 2.8, “Are we there yet? Has System Assembly from IP Blocks Become Like Connecting LEGO Blocks?” on Tuesday and moderating panel 10.8, “Embedded Software Testing: What Kind of Problem is This?” on Thursday.

The other thing that would be nice to be at DATE 2010 for would be to hang about the Springer booth which should be selling (and I hope selling out) the new book by Brian Bailey and myself, “ESL Models and their Application:  Electronic System Level Design and Verification in Practice“.   If you are there and buy it, I hope you find it useful (of course, you can buy it online at the Springer site and at places like Amazon).

But beyond my own concerns, DATE has many interesting things to offer attendees.  Other technical sessions that look interesting to me are:

• Keynotes by Alberto Sangiovanni-Vincentelli and Herman Eul
• Session 3.4, “Application Development for Multicores”
• Session 8.3, “System Modelling for Design Space Exploration and Validation”
• Session 9.3, “Language Based Approaches to System Level Design”
• Session 10.4, “Architectures for Next Generation Wireless Communication”

But check out the programme for yourself – there is lots of interest.  With tutorials on Monday and workshops on Friday, you could spend a technically rewarding and very busy week in Dresden.

If you manage to get to DATE I hope you can leave a comment about it here.  I’ll be interested in hearing how it goes.