Taken for Granted

It is a truism in Silicon Valley and most other places where engineers congregate, that if you want to get a good crowd out to an event, offer them a free lunch.  The Low Power Design Summit, sponsored by Cadence’s Power Forward Initiative, and held on Wednesday October 1 at Cadence, San Jose, was no exception.

Pieter Brueghel the Elder, The Peasant Wedding, 1567-1568

However, in this case, seeing the large crowds (at least 200 people during the day by my quick reckoning, sometimes in one room and sometimes split into two tracks) and the number of questions asked during some of the presentations, I think it was a toss up between the interest in low power, and the CPF and the tool flows from Cadence and other tool suppliers that support it, and the interest in a free lunch!

One thing that is pretty likely in events of this kind is a fair degree of marketing as opposed to purely technical presentations.  However, this can still be quite useful to give an update on various technologies and how they are being used, and a fair trade for the attendees’ time as long as the event is free.  There were a number of nuggets presented during the day that rewarded attendance.  (Another thing I enjoyed was the chance to help fill in the Cadence history chart in their cafeteria with some items of Alta history from the late 1990s).

It was clear from the presentations from many IP suppliers and users are applying CPF in a very practical way.  It was also interesting that the other Elephant in the room (perhaps not the best analogy since there the US elections are on right now) is the competing UPF format.   It was only in the morning panel when Ameesh Desai of LSI mentioned the competing UPF format (and the extra work involved in supporting both) that the other Elephant was acknowledged.   It is also unclear what the usage status of UPF among real users and IP suppliers currently is, although I am sure the UPF supporters will continue to talk about that.

Perhaps the most interesting part of the day was the morning panel “Deploying Low Power - What are the Challenges?”, moderated by Susan Runowicz-Smith of Cadence and featuring Ameesh Desai of LSI as noted, Anis Jarrar of Freescael, Herve Menager of NXP and Brani Buric of Virage Logic.  One of the things I was most interested in were the questions and discussions of whether system level was being added to the low power flows, and whether work was progressing on filling in this gap.  A very interesting perspective on this was the question:

How much better than Excel can a system level power tool be?

The gap was acknowledged, but the way forward seems unclear.  Perhaps readers may have comments on how to fill in the system level power gap in the flows.

Near the end of the afternoon, Carl Guardino of the Silicon Valley Leadership Group gave a quick talk on Green initiatives and prospects in the Bay area.   This was very interesting and the SVLG gave out booklets “Clean and Green” , their 2009 Silicon Valley projections covering the environment, energy, transportation, workforce, housing, health care and tax policy.  My favouriite wish - BART to the south bay, was covered along with many other ideas, initiatives and projections.  You can download and read the plan at the links.  Perhaps the best quote in the whole day was one Carl Guardino repeated from David Packard, who helped found the Silicon Valley Leadership Group 30 years ago - this should be a watchword for us all:

When you do something well, don’t gloat about it. Go out and find something harder and better to do.

The organisers promise to have versions of the presentations posted at Power Forward soon.

This post is a shameless plug for ESWeek 2008 in Atlanta, Georgia, October 19-24. ESWeek stands for “Embedded Systems Week” and it is an amalgamation of three major conferences - CODES+ISSS, CASES, and EMSOFT - and several workshops on the Sunday and the Thursday-Friday of the week. I have a vested interest in ESWeek as this year I am the programme co-chair for the CODES+ISSS sub-conference. One nice feature of ESWeek is that although you state a primary conference when you register, you are able to attend any of the sessions from all three (workshops are extra). And the advanced registration deadline, where you save money on registration, has been extended to September 30. The technical programme, which you can find here, includes many interesting talks and events.

Cover of “The Embedding”, science fiction novel by Ian Watson (1973)

So come and be embedded in Atlanta! I hope to see you there.

I am sure everyone knows the old saying “When all you have is a hammer, everything looks like a nail.” This is a natural tendency of everyone with a solution to a problem: to assume that their solution is one fit for every problem. I was reminded of this when I read two interesting posts on the DAC Ezine: Sunil Ashtaputre of Synofora on “Algorithmic Synthesis: the “Killer App” for broad ESL deployment”, and Mike Meredith of Forte Design Systems on “ESL Synthesis Innovation: the importance of choosing the right technology”.

Georges de la Tour, St. Joseph, the Carpenter, 1640s (the Louvre)

The columns by Sunil and Mike are both interesting, but both take a bit of a narrow view of ESL and ESL synthesis. Algorithms described by C can be more than a front-end for hardware-oriented ESL synthesis - they can be used automatically or manually to configure a processor that is precisely tuned to the particular algorithm, and may give performance 10-100X faster and energy consumption 70-90% less than running this algorithm on a standard fixed Instruction Set Architecture (ISA) processor. These methods are now well proven in many different applications.

And when Mike Meredith talks about ESL or High-Level Synthesis methods, he talks about a variety of input methods, among other differences, and cites:

Input approaches include SystemC, C, C++, ARM object code, graphical methods and proprietary languages such as Haste, nML, TIE, BSV, Matlab, SystemRDL, and LISA.

However, he is not really comparing apples and apples here. Input languages such as nML, TIE, and LISA are used to describe the instruction sets or parts of the instruction sets, and other characteristics, of processors, often to be generated via an automated processor generation flow. These may be fairly generic in their instruction set, or highly application specific. Although some automated processor generation tools will take a C program as input and generate a configured, extended, application specific processor (ASIP) as an output, this is an alternative to classical High-Level synthesis, not really comparable to hardware-oriented HLS. Among other differences, any of the generated processors is usually able to run any C code, even C code vastly different from the C code that may have been used to configure the processor.

It’s good to compare different approaches to implementing functionality defined in C/C++ or other high level languages in an application oriented way, but it is important to remember that the different methods on offer represent different points in a pretty wide tradeoff space. And one person’s apple is another person’s orange!

Comments?

Vincent Van Gogh, Still Life with Fruit (The Art Institute of Chicago)

I have been quite busy for a little while and haven’t posted for a bit. I’ve also been trying to figure out a way to stop spambot comments on this blog, as they have been escalating from a few a day to 30-40 a day, to over 250 a day this past weekend. Luckily comments are moderated, but in attempting to manage the flood of the last few days I managed to accidentally wipe out several legitimate comments from August! (My apologies to the commenters).

In the meantime I note that the submission deadline for DATE 2009 conference in Nice next year is fast approaching. The deadline is Sunday September 7 for papers, special session, tutorial and workshop proposals.

DATE (Design Automation and Test in Europe) has had a strong and growing role in presenting the latest work in system-level design in particular, and always has an interesting programme. I am serving as topic co-chair this year on the programme committee for area D1: System Specification and Modelling, and would encourage you to consider submitting to that area. But there are many other areas of interest and you should consider submitting to the conference, especially if you have been writing up your work and wondering where to submit it to. Nice in April 2009 should be a particularly “nice” location for the conference, as it was in 2007.

Further information on DATE 2009 can be found at their web site.

First, for full disclosure, I would like to mention that I am on the board of Cadstone, a commercial company founded by Perry Alexander to develop Rosetta-based tools and models and offer services. I have also been involved with Rosetta on and off for over a decade, and wrote the foreword for Perry’s book.

Jean-Francois Champollion, painted by Leon Cogniet, 1831: Champollion is credited with deciphering Egyptian hieroglyphics including part of the Rosetta stone in 1822

Many of you may not have heard of Rosetta. This is the ultimate outgrowth of a series of developments aimed at creating a system level design language that started with a meeting in Dallas in 1997. The aims of Rosetta are quite different than those of imperative ESL languages such as SystemC and lower level languages such as SystemVerilog. Indeed, despite the use of ‘System’ in SystemC and SystemVerilog, one can make a good argument that neither of these languages is a ‘true’ system level language at all. And one can also make a good case that ESL = Electronic System Level is a misnomer. This is partly due to the very amorphous nature of the word ’system’ - for example, one designer’s ’system’ is another designer’s ‘component’; more colloquially, “it all depends on what your definition of ’system’ is”. Nevertheless, when you consider a ’system’ in all its aspects, including declarative properties, constraints, assumptions, performance envelopes, and other non-functional aspects of all types; and conceive of systems including biological, electronic, software, mechanical, and industrial elements, ranging in scale all the way up to our largest works of infrastructure, it is clear that ‘true’ system design embraces many aspects not dreamt of in the philosophies of ESL, SystemC, SystemVerilog, and the commercial EDA and ESL industries. Dealing with at least some of these aspects and attributes is something Rosetta was designed to embrace.

For those interested in more information on Rosetta, there are several good references:

1. the book by Perry Alexander, “System-Level Design with Rosetta”, Elsevier Morgan Kaufmann, 2007.
2. the Rosetta web site, maintained by Perry Alexander on behalf of the group working on Rosetta, which is going through standardisation (as P1699) via the IEEE DASC (Design Automation Standards Committee).
3. at least two companies are working on Rosetta-based tools: EDAptive, and Cadstone
4. a Google Tech Talk , “Security as a System Level Constraint”, given by Perry Alexander on June 6, 2008, available on YouTube

For those of you attending FDL 2008 in Stuttgart, Germany, September 23-25, there will be a couple of interesting sessions:

• A tutorial by Perry Alexander on Rosetta, Tuesday September 23, 1430-1600
• A Session on “System Level Specification Using the Rosetta Language”, Tuesday September 23, 1630-1800

Finally, I would like to mention one of the interesting avenues that Rosetta work is now taking, leading it to a different place than traditional EDA/ESL, but one that may be of interest to true, higher level, full system designers. This is work being done to model aspects of Software-Defined Radio (SDR). In fact, the Rosetta web site has some recently added model examples in the SDR domain that are worth a look.

Some of you may be familiar with Leibson’s Law (by my colleague Steve Leibson):

Leibson’s Law: It takes 10 years for any disruptive technology to become pervasive in the design community.

Rosetta may be an interesting example of a ‘double Leibson’, given that it started in 1997 and is already past its 10 years, with some way to go before becoming widely used (assuming its long term success). This may be due to its scope and ambition and the heterogeneous nature of “systems” more than anything else.

The open question that heads this blog is “is Rosetta ready for ‘true’ system level design?”. The answer can only come from systems designers and researchers taking a look at what has been done with the language, examples using it and where it is going. Knowing what needs to be done or is still missing is an important part of shaping its evolution. I am certainly interested in your comments on this topic, as I know the Rosetta committee and others will be.

My colleague Patrick Madden, a professor of computer science at Binghamton University in New York, is a great fan of Amdahl’s Law, and in fact writes a blog of that name. His main argument is that Amdahl’s Law, which limits the speedup possible on an application ported or written for a multicore processor to the (easily) parallelisable part of the application, means that the pendulum of the computing industry has swung far too much to the “multicore” phenomenon of recent years, and is now ignoring potential improvement in single processor performance that would have an impact on many applications not-so-easily parallelised.

In my discussions with Patrick I think we have agreed that the world divides into different parts, and as my colleague Steve Leibson and I have discussed, there are many application and product spaces that can make use of multiple heterogeneous ASIPs - applications that demonstrate “convenient concurrency“. This is especially true in areas such as multimedia image processing, multi-functional portable devices of all kinds, and networking, as well as certain domains in high performance computing. However, I do agree with Patrick that there are other kinds of applications that could be called “stubbornly sequential”, and may best be solved, with our current state of understanding and knowledge, by a faster uni-processor, assuming one could be built.

With that in mind, Patrick has issued a challenge which you can read about at his blog: “Take $1000 out of my pocket for Thinking Parallel”, for someone who can come up with a parallel multicore implementation of the shortest path problem, that beats Dijkstra’s serial algorithm, on a challenge called the 9th. DIMACS Implementation Challenge for Shortest Path. Read more about it at Patrick’s Blog! But please comment on it here if you would like.

The other day I was emailing back and forth with my colleague Steve Leibson about the new Cadence ESL synthesis tool. He commented that there seems to be a gap between IP-centric design (such as processor-centric design, or the use of other large configurable IP blocks) and the general ESL world - for example ESL synthesis, which assumes for the most part that you are implementing a piece of functionality entirely in a new dedicated hardware block or blocks. To quote Steve,

A good tool would be able to decide when to use a configurable processor core to implement a block in a hierarchy and when to generate new RTL instead.

Coincidentally, Frank Schirrmeister was musing in the same direction in his recent blog on ESL synthesis. He points out many options for designing a major complex function at high level, concentrating on the topology and interconnect, and many options for designing each major block of functionality from pure software on a fixed ISA processor through to RTL synthesis, leading to at least 35 permutations and options for “function to implementation”. Design space exploration indeed!

Johannes Vermeer, The Astronomer, c. 1668

Early astronomers as pictured here had star charts, globes and early telescopes. Perhaps with processor-centric ASIP design and ESL synthesis we are still in this early stage of development. It seems to me that considerable opportunities lie, as Steve said, for the development of design space exploration tools that link into the various implementation flows from various vendors and for various alternatives and allow people to really explore space effectively. Perhaps a DSE version of the Hubble Space Telescope - without the early optical flaw that necessitated sending a repair crew out into space!

My colleague and friend Steve Leibson writes a blog for EDN, “Leibson’s Law”, in which he discusses many items relating to his informal law:

Leibson’s Law: It takes 10 years for any disruptive technology to become pervasive in the design community.

In this case, I wonder if Cadence’s announcement today (July 14, 2008) that it has returned to the ESL Synthesis arena with its new C-to-Silicon Compiler tool, along with the corollary announcement from Calypto about linking their SLEC System-HLS tool with the new Cadence tool, is a case of Leibson’s Law in action.

Rembrandt van Rijn, The Return of the Prodigal Son, 1669, The Hermitage Museum, St. Petersburg, Russia

There are good writeups about this new tool that was done by an incubator team under the name “Project Sydney” that contained several people from Cadence Labs, Berkeley. Two on the web are by Richard Goering at SCD Source and Ron Wilson at EDN. (It was also telegraphed conceptually a week ago by Mike McNamara in an article “ESL Handoff: closer than you think”, on EDA DesignLine online). Among the features discussed as part of this new tool are an ability to deal with design hierarchy, an ability to mix control and dataflow to new levels, incremental synthesis, and an embedding of Cadence’s RTL compiler or a subset of it in the tool to improve results, especially for control. I will be interested to see more about user reaction and evaluations of the tool, but note that Cadence, Renasas and Hitachi have worked together on the tool for a significant period prior to today’s announcement. It will also be interesting to see how it fares against the competition from Mentor Catapult, Forte Cynthesizer, Synfora, Bluespec, AutoESL, and others in the high-level synthesis field, which is relatively crowded at this point.

More interesting, perhaps, on a higher level, is what this return of Cadence to ESL design (not “Enterprise System Level”, but real ESL design) means for ESL in general. It is now a decade, give or take a couple of years, since Cadence absorbed its pioneering Alta Group subsidiary back into the Cadence main stream. It is coming up for 5 years since Cadence moved what was left of its pioneering system-level tool team over to CoWare. If Cadence’s return to the ESL design arena is an indicator that ESL has begun to enter a mainstream phase (or as Leibson’s Law would have it, begin to become pervasive in the design community), then that is a good marker for ESL and adoption. Coming after last week’s announcement that Carbon Design Systems was picking up the SOC Designer tool and much of the development team from ARM, thus breathing new life into that tool, these signs of change in ESL may be welcome signs of mainstreaming.

As usual, “time will tell”!

In the “good old days” of business trips, before the internet and cellphones, sometimes a business trip could actually include a large element of travel. That is, in between the meetings there might be time to actually see some interesting historical or cultural sights in the cities and countries one was visiting. With a fortuitous schedule and a few cancelled meetings, a fair bit of sightseeing could be managed.

Such is not the case with today’s business travel. Between jet lag, the internet and cellphones it is all too easy to fill 100% of all your waking time (and given jet lag, sleeping time too) with meetings, emails, phone calls and being “on” all the time. At 2 AM there is always one more project to start or finish, one more email to respond to, one more crisis to manage.

As a result, in the last few years the only way I have been able to really see a place is to take a holiday there - without cell phones and computers. The last 1.5 weeks my wife and I were fortunate to visit Kyoto in Japan, and we had an extremely interesting time there. Kyoto has what seems to be hundreds of temples and shrines, museums and historical sites, and it’s also very easy to take trains from there to other sites (one that we particularly enjoyed was visiting Himeji Castle).

Old painting of Himeji Castle

While travelling in Kyoto and other parts of Japan, I did my best to totally wipe my mind clean of embedded processors, ESL, system level design and everything else to do with work. While I didn’t totally succeed, it was a very relaxing vacation.

Now that I’m back, I’m slowly re-immersing myself into everything embedded and ESL (noting that the Cadence-Mentor takeover battle did not make any real progress while I was away, and reading the very interesting series of blogs that my colleague Steve Leibson posted on the MPSoC 2008 conference in Maastricht, and writing a few comments on them too).

Back into the swing of things tomorrow, and I’ll write a more substantive comment when I have something to say! In the meantime, I heartily recommend vacations….

I’m no Nostradamus, and was of course taken by surprise with the rest of the electronics world when on Monday June 16 I heard that Cadence was going to try to do a hostile takeover of Mentor Graphics.

Carlo Antonio Tavella, Jonah and the whale, mid-17th. century

Cadence has had a long-chequered history in ESL, starting with the formation of the Alta group (where I used to work) in the mid-1990’s. After building Alta up to one of the biggest ESL groups in EDA, Cadence then wound it down through a series of “interesting” management decisions, eventually trading the remnant - primarily SPW - to CoWare who used it to broaden their scope of tools, and which provided a much more supportive environment. Cadence then went through a stage of denial, a stage of re-definition (trying, somewhat lamely, to redefine ESL as “Enterprise System Level”), and then embarked on some new R&D initiatives which have been kept mostly quiet for several years. One of these is in the area of high-level synthesis, and was discussed by Mitch Weaver of Cadence in 2004, as being a combination of Get2Chip behavioural synthesis technology together with Cadence Labs research, and with the promise that “Next year [... 2005 ...] you’ll hear some big news from us.” We had to wait another three years, but in April 2008 Mike Fister in a talk in Japan revealed more details about Cadence’s re-entry into “Upstream Design” (See “Cadence announces reentry into upstream design in Japan“). Here he talked about a SystemC-based high level synthesis tool which has been in evaluation in Japan for a year, and also alluded to other tools under the mysterious label “Sydney”.

Mentor Graphics has had a grab-bag of different tools in the ESL domain for many years including some they acquired when they bought Summit Design, but these have never been knit together into a common ESL toolset driven by a common design approach. Just looking at their website, we can see point tools such as their flagship high level synthesis tool Catapult, IP-based design assembly Platform Express, Visual Elite, and Vista (both from Summit) for capture and simulation in SystemC, a seemingly overlapping tool called System Architect, HW-SW coverification with Seamless (clearly now put under verification, along with the Questa tools), UML modelling with Bridgepoint, and the specialised automotive system design tool Volcano.

Chris Edwards drew an interesting diagram on one of his blogs illustrating the overlaps and complementary tools between Cadence and Mentor. (”Overlaps R US“). This shows Catapult vs. Project Sydney, although from Mike Fister’s comments in Japan, Project Sydney seems to have a wider scope. The other Mentor ESL tools, although not listed, seem complementary and not overlapping.  [UPDATE 22 June 2008:   Chris Edwards has updated his very useful chart to include several of the other ESL tools, and they are complementary, not overlapping].

So what will happen in ESL if Cadence buys Mentor? As I noted in the beginning, I’m no Nostradamus! No doubt the non-overlapping tools will be judged on a tool by tool basis to decide their worth as businesses and as technologies. With respect to Mentor Catapult vs. the Cadence high level synthesis project, no doubt the evaluation criteria will include relative market penetration and interest, quality of results, and the future of the technology as a basis for further development. The decision, of course, will be made by those in the combined company responsible for the ESL domain.