20  Jun
How Low Can We Go?

In an article this week in one of the industry trade publications, an iSuppli source was quoted as saying, “The usable limit for semiconductor process technology will be reached when chip process geometries shrink to be smaller than 20 nm, to 18-nm nodes.” According to iSuppli, this will occur in 2014 when Moore’s Law will not drive volume production. This is an interesting take on the divergence of Moore’s Law and the economics of the semiconductor industry.

The technological advancements of the semiconductor industry have amazed me for as long as I have worked in it. I remember transistors with five-micron features in the early 1970s and a worry at Texas Instruments about having equipment available for volume IC production much beyond that point. During the intervening 35 years or so, various industry visionaries have predicted a “practical” limit to process node shrinkage for a variety of reasons – manufacturing capability boundaries, design limitations, and even a physics-based stopping point; I believe Carver Mead set the latter at around 10nm. Now we have another factor to consider when contemplating the silicon “wall” – economics.

iSuppli postulates that process node shrinkage won’t be limited by the ability to make devices smaller (through shrinking feature sizes). Instead, it will become too expensive for most chips to utilize a process node below 18-20nm. This is an interesting concept, but not a really surprising one. Mature process nodes are much more economical to use than leading-edge ones; the older nodes have already gone through the roughly 30% learning curve (and price reduction) per year for the first few years. And while leading-edge process development is necessary for continuing the advancement of the chip industry, most products do not need to be fabricated at 45nm and beyond to show a good profit margin and, in fact, certain chips such as analog and mixed signal devices do better at the larger process nodes.

So, do I agree with iSuppli’s analysis? Pretty much so, although the 2014 date and 18-20nm node size may be off. In addition, some new and highly innovative silicon (or other semiconductor) structure may come along and throw everything out of whack.

That’s what makes working on our industry so much fun!

Posted by admin, filed under Uncategorized. Date: June 20, 2009, 7:17 pm | No Comments »

If you are like me, trying to get all the information you need to do your job can be a harrowing experience. With so many sources from which to choose, how do you know which ones are right for you to stay current? Well, a little help is on the way in the form of a DAC panel, “Tweet, Blog or News: How Do I Stay Current?”

Presented as a Pavilion Panel Wednesday afternoon on the DAC show floor, this will be more like a roundtable than a true panel, with a moderator, three participants and no slides. The panel’s goal will be to help you understand the various information sources you have available – including traditional ones such as print and online publications along with the newer blogs, portals and social media networks – and what each has to offer.

Each of the three panelists will give a position statement, followed by a group discussion on topics such as how to find your way around the various information sources, what tools are available to use these sources and what is the best way to use them. The panelists will even give some advice on how to start blogging.

There is an overabundance of things to see and do at DAC, but I would put aside the Wednesday, July 29, 4-5PM slot to sit in on this panel. The topic is interesting, timely and, who knows, you might pick up some pointers on how to make your job easier. Check out the panel details at: http://www.dac.com/events/eventdetails.aspx?id=95-106

Posted by admin, filed under Uncategorized. Date: June 9, 2009, 2:23 pm | No Comments »