It was a busy week in Silicon Valley recently with two interesting and free one-day events taking place two days apart, the Common Platform Tech Forum and the GSA Expo. These types of events, financed by sponsorships and exhibitors, allow attendees to obtain a lot of information about industry segments and, often, trends in a relatively short time. Having attended both, I came to a conclusion – there are some interesting developments taking place in the options you have available for chip processing.

The birth and growth of the independent semiconductor foundry business several years ago marked a change in how chip developers could have their designs processed. Up until then, the rapidly rising cost of a silicon processing facility meant that only the largest semiconductor companies could afford to have wafer fabs dedicated to leading-edge silicon processes. By utilizing economies of scale achieved from processing chips from several companies, pure-play foundries fueled the growth of the fabless semiconductor industry and allowed even very small (and often highly innovative) chip companies to bring their products to market.

Besides taking advantage of volume wafer processing, successful foundries were also able to achieve business clout and bargaining status by developing partnerships with EDA, IP and design services organizations. This permitted the foundries to take on the role of “one-stop shops? for many of their customers. In fact, IP and EDA relationships often defined the value-added features of one foundry over another.

The Common Platform consortium represents, to me, further evolution in semiconductor process availability. Developing silicon processes that can go to multiple foundries, in this case IBM, Chartered and Samsung, gives customers flexibility in where they manufacture chips and also solves the problem for many companies of having a second wafer processing source. But the Consortium has gone beyond multiple foundry availability. With a Joint Development Alliance that includes Freescale Semiconductor, Infineon, ST Microelectronics and Toshiba, the Consortium has added valuable knowledge and experience in advanced chip design, which they use in the development of next-generation process nodes, currently targeted to 32nm and 28nm. The Alliance is what gives the Common Platform Consortium an edge over pure-play foundries such as TSMC and UMC in process node development.

The GSA Expo, a broad gathering of EDA vendors, foundries, IP developers and chip companies, offers a large group of exhibitors along with several keynotes and technical sessions covering a wide range of semiconductor topics. As in past years, I find the GSA Expo a good place to discuss industry trends and issues with colleagues, such as the pluses and minuses of pure-play foundries vs. process-platform consortiums.

I think the Common Platform model is a good one and will no doubt lead to the formation of other successful process development consortiums down the road. If nothing else, these cooperative efforts in process node development will put pressure on the pure-play foundries to stay on their toes and not get complacent about their R&D efforts.

Posted by admin, filed under Uncategorized. Date: October 11, 2008, 9:07 pm | No Comments »