At the Design Automation Conference earlier this month, I participated in a breakfast roundtable to discuss the ease (or lack thereof) of integrating third-party silicon IP into a design. Details on the roundtable were discussed in my last blog (June 4), but my co-participants – Steve Leibson of Tensilica, Adam Traidman of ChipEstimate.com and Navraj Nandra of Synopsys – and I were fairly consistent in our view that if will be very difficult to make third-party IP integration a turnkey operation.
At this time there appear to be three obstacles to “easy� IP implementation on a chip: lack of standardization about what constitutes quality IP and a “good� IP supplier; the fact that every reuse of a piece of IP constitutes putting the IP into a different system environment on the chip, each with its own unique interface and timing considerations; and IP and overall chip complexity continue to increase as process nodes shrink. Furthermore, when you consider analog/mixed-signal IP, the IP integration task becomes even more daunting.
The first barrier to turnkey IP integration, lack of standardization, was addressed for a time by the now dissolved VSIA. While the Alliance made progress in IP qualification standardization, no one as yet has successfully continued this development although the IEEE, which picked up the VSIA work, should show some further improvement in qualification standards down the road. What are also needed are customers who demand a global quality IP standard for selecting IP and IP vendors; right now, too many companies rely on internal means of gauging quality
Successful IP reuse will continue to be a problem due to system-level issues when implementing IP in an SoC. As much as we would like to think that we can treat IP as a separate entity, there are too many interactions on the chip to do so – each SoC represents a different set of requirements for IP integration and verification.
Finally, as IP and overall chip complexity continues to grow, there is an increasing need for better “system-like� tools that operate on an SoC and its blocks. Such tools will eventually be available for IP integration, but what is available currently is not adequate.
So, yes, my short-term view of turnkey IP integration is a negative one. An IP supplier must become more of a partner to the IP integrator and not just a supplier of IP. The suppliers, along with possible third-party “IP integration facilitators,� similar to design houses but focusing on IP implementation, must provide a higher level of service to the integrators. In other words, look at the absence of a turnkey IP integration methodology as an opportunity for more engineering jobs in the semiconductor industry.