Tuning into Jim

Part of the fun of attending DAC every year is going to several of the events that are not “DAC sponsored,� in other words, events that are put together and sponsored by companies, analyst groups, standards organizations and the like.  Very often these turn out to be some of the highlights of the “DAC experience.�  The following list contains a few of the unofficial DAC activities that caught my eye and I plan on attending.

·         EDAC Executive Reception, Sunday 5-7PM at the Marriott.  This was originally the Sunday Dataquest briefing, the unofficial opening of DAC, we all loved for networking and informational purposes.  Register at http://www.edac.org/invites/dac_reception_07.htm?opendocument

·         Gary Smith (now at Gary Smith EDA) is back the same evening, also at the Marriott, from 7-8:30PM, to discuss EDA trends and numbers.  Register for this at https://app.e2ma.net/app/view:Join/signupId:20318

·         VSIA, the IP standards alliance, has a luncheon on Tuesday from noon to 1:30PM in Room 32AB on “IP Quality: How to rate IP using VSIA’s QIP Metric standard.â€?  Mentor, Denali and LSI will all make presentations and you can register at http://www.vsia.org/events/DAC2007Registration.htm

·         Tuesday will feature the always popular Denali party – nothing else need to be said about this except to register for your (limited supply) ticket at https://www.denali.com/docs/servlet/denalisoft.dac.Rsvp 

·         MOSAID and Sidense are sponsoring a very interesting panel lunch on Wednesday from Noon until 1:30PM in Room 29CD on “Solving the SoC Memory Puzzle.  The moderator will be the knowledgeable and entertaining Ron Wilson, EDN’s executive editor.  Register on the MOSAID website at http://www.mosaid.com/corporate/products-services/ip/dac_register.php

·         Accellera, the standards committee that works on design languages and methodology, is hosting a breakfast and panel discussion on Wednesday morning, 7:30-9AM in Room 26AB on IP: The Next Frontier for SystemVerilog.  Sponsored by Denali, you can register at http://www.accellera.org/events/register

A couple of weeks ago, EE Times reported that market research firm Semico announced that Structured ASICs were still strong and had the potential for “explosive growth� in the future.  This surprises me – a lot!

 

Despite a promising beginning, and originally backed by several major semiconductor companies, Structured ASICs have never reached the levels predicted by many analysts three years ago.  There are several reasons for the less-than-expected growth in this segment, including non-agreement of what comprises a Structured ASIC; greatly different architectures and technologies offered by the professed Structured ASIC vendors (some FPGA-like, some ASIC-like and some in-between); pressure on the high-end from ASICs with new, lower cost business models and on the low-end from FPGAs; and lack of tool support from the major EDA companies.  Then came the pullout of chip vendor LSI Corp. (then LSI Logic) in early 2006, quickly followed by tool vendor Synplicity, from the Structured ASIC market.

 

So – why the optimism of Semico in the future of Structured ASICs?  It may (at least partially) be due to, as EE Times states, Semico creating a definition that it said ‘captures most of the important features’ that can be used to define a structured ASIC.  The EE Times article then goes on to list what these features are and, upon reviewing them, they sound to me a lot like what comprises an ASIC or ASSP.  With this definition, Semico predicts a compound annual growth rate of 28.2 percent in the years 2007 through 2011. How “real� is this growth?  Well, by Semico’s current Structured ASIC ‘definition’ a lot better than it would be based on what I remember as defining a Structured ASIC.  Me – I’m not nearly as optimistic about Structured ASIC’s future.  The market segment may not be dead, but it currently sure doesn’t have a high quality of life. 

That’s my opinion – let me know what yours is.