Engineering is all about innovation, be it the evolutionary type which incrementally advances technology, or revolutionary – a disruptive force that changes the way the electronics industry develops products.  Today, we will consider the latter and whether or not EDA tool vendors do their part in supporting new, highly innovative ways of turning out chips.


The short answer to this question is – sometimes.  When HDLs started entering the semiconductor design flow as a way of doing digital chip design in the mid-1980s, Synopsys pioneered the development of commercial logic synthesis tools that used these languages to greatly increase designer productivity.  Other EDA companies followed suit with their own synthesis tools and HDL-based design became the standard way of dealing with chips that had become too complex to develop by prior schematic-based techniques.  Logic synthesis is thus a good example of the EDA vendor community embracing and sustaining a new design methodology.  On the flip side, let’s look at a couple of examples of disruptive design innovations that have not been as well supported.


As increasing chip clock frequencies started to generate difficult-to-manage power dissipation and signal integrity problems, designers turned to multicore processor chips to reduce these problems.  However, one of the major complaints of multicore chip designers is lack of adequate tools to design and debug such designs.  By and large, the major EDA vendors have not yet introduced multicore design tools into the market that can handle the types of high-performance multicore architectures companies such as Cradle Technologies, TI and IBM, have brought to the market.  This task has fallen to some niche EDA tool vendors.  The companies that have developed these new architectures are also developing the design tools for them.  The performance and ease of use of these tools have a major impact on the acceptance of the architectures that they support.


As another example, just a couple of years ago Structured/Platform ASICs were “hot,? being touted as a way to reach ASIC-like performance with sharply reduced time-to-market and NRE costs.  Unfortunately, several factors have led to a sharp reduction in their popularity, including being squeezed by FPGAs on one side and mid-range ASICs, fueled by new business models with lower NREs and shorter design times, on the other.  A lack of development tool support by the “Big Three? EDA vendors also has been a contributing factor to the demise of these architectures and many of the original Structured/Platform ASIC vendors are now out of the this market, along with several other EDA vendors who had, at one time, offered good EDA tool support.


Admittedly, putting in the resources to support highly innovative technology is very chancy for the EDA vendor community and can be an expensive endeavor with low returns.  However, you have to take risks if you want the chance to reap the benefits of a successful new technology.  Along with Synopsys, other large EDA vendors such as Mentor and Cadence used to be more active in backing early technology endeavors.  Synplicity, with their pioneering FPGA development tools, is a prime example of how “backing the right horse? can pay off.  It’s time for the leading EDA vendors to once again play a bigger role in supporting new technologies at their early stages.

Posted by admin, filed under Uncategorized. Date: March 13, 2007, 12:34 pm | No Comments »