Tuning into Jim

Over the past several months, semiconductor foundries have been going all out to promote themselves and their partners. Two of the Big Boys – TSMC and GLOBALFOUNDRIES – have been spending lots of money on their own shows and on making appearances at others.

Both TSMC and GF (the only major foundries at DAC) set up large partner areas where multiple IP, EDA and other partner companies had tabletop displays and kiosks and made presentations to the attendees. More significant, however, are the efforts of both companies in sponsoring their own technical symposiums, free to attendees. TMSC had a total of nine symposiums worldwide, an increase of what they sponsored last year. GF is preparing to have a Silicon Valley technical conference on September 1, which will fill a gap left by the cancellation/postponement of the Common Platform technical conference.

This uptick in foundry-sponsored conferences and symposiums is good news to their various partners, particularly those in the IP provider space, and to attendees, since these people are focused on everything available to help them do their chip designs. Attendees appreciate seeing and considering IP from the partners at a foundry conference as a “nod of approval.” Nowadays “show me the silicon” is a requirement for many semiconductor developers, and having several of a foundry’s silicon partners available in a common venue is a win-win-win (foundry-silicon partner-customer) situation.

Beyond processing expertise and pricing, a foundry’s “partner community” is an important factor that helps differentiate itself from its competitors. Expanding this community and spending the money to make it available to the semiconductor design community at-large through symposiums and conferences is a positive sign that the semiconductor industry is moving upward.

As I’ve mentioned in previous blogs, one of the fun things to do at technical conferences is to sit in on an event that is not an ‘official’ conference session. These events often include talks and/or panels on interesting topics and are sponsored by companies who offer products or services associated with those topics. Such was the case this week at the Embedded Systems Conference, where I attended a luncheon sponsored by Synapse (www.synapse.com) with participation by Atmel, Silicon Labs and California Eastern Labs (CEL). The topic: “The tipping point for wireless M2M communications.”

Synapse makes mesh network operating systems and middlewear for the wireless mesh network market while the other three companies embed Synapse operating systems in some of their processors or microcontrollers. All four companies delivered presentations that helped me better understand IEEE 802.15.4 and ZigBee for low-cost, low-power M2M communications. I also learned about an existing standard – RF4CE (Radio Frequency for Consumer Electronics) – geared at using RF in appliance remote controls instead of the traditional IR for better reliability, to overcome line-of-sight limitations and in some applications where IR controls just won’t work, such as with strongly back-lit monitors.

Particularly interesting was the breadth of applications targeted by 802.15.4-enabled devices. Home and industrial remote lighting, crop irrigation, public thoroughfare lighting, smart utility meters, smart energy such as solar and LED, home entertainment devices, industrial security systems, and asset management are just a few of the applications where 802.15.4 is becoming pervasive. And forget the idea that 802.15.4 is for short-range applications. Companies such as CEL are making devices with ranges beyond two miles.

All-in-all, a nice way to spend a lunch hour, getting an update on some communication protocols that will impact all of our lives and learning about new and interesting products that support these protocols. This is the type of event at which I don’t mind a sales pitch that goes along with the educational material.

I think the San Jose version of the annual TSMC Technology Symposium this past week is a good indicator of where the semiconductor industry is going over the next few years. The positive growth predictions of keynote speaker Morris Chang, TSMC founder, chairman and CEO – 22% this year and 7% in 2011 – are only one gauge of industry direction. Another is what happens on the exhibit floor.

As in past years, there were plenty of companies willing to put out the money and resources for an exhibit floor booth in San Jose (which also includes smaller, tabletop exhibits this month in Austin and Boston). From a potential customer perspective, foundry-driven shows such as the TSMC symposiums provide an excellent opportunity to meet prospects who are, largely, in the chip design business. Since my company, Sidense, is an IP provider, this is a good audience for us. However, the number of exhibitors is not a great measure of industry direction – the attendee base serves this purpose.

TSMC host Chuck Byers, a familiar face at the TSMC events, indicted that advance attendance was down a little this year, but that walk-ins could make up the difference. Judging from the lack of empty seats for the presentations and the traffic on the show floor, I believe that this was the case. The intangible “show floor energy” was high, demonstrating a positive attitude among attendees. More importantly, we and some of the other exhibitors with whom I compared notes found that visitors had a high level of interest in IP and tools available to help them ratchet up their design productivity. This was in contrast to the more cautious “wait and see” posture of prospects six months to a year ago.

The bottom line is that things are definitely improving. Customers seem more willing to spend money now to gain competitive advantages than they were a year ago. While this doesn’t mean that we are solidly on the road to recovery, I do think that it shows that we have already hit the bottom of the economic trough and that we are making moderate progress on our way to a more normal business environment. However, unfortunately, this doesn’t include, at least at this time, a large surge in hiring to make up for jobs lost over the past two years. That will take a while longer.

While many third-party organizations conceived and launched to assist both semiconductor IP vendors and users have gone by the wayside (think VCX and VSIA, for example), the need for such groups has certainly not gone away. In fact, due to the breadth of available IP and the increase in SoC complexity, this requirement is now even stronger.

IP creation, evaluation and integration suffer from a lack of standards and the purchase of IP of almost any complexity requires better-than-average communication between vendor and user. It’s this need that makes the Constellations program, initiated by IPextreme and a small core of charter members, so compelling.

Originally conceived as a sales collaboration effort between small IP vendors, Constellations is in the process of rethinking its goals and expanding into other member-cooperative efforts that will, ultimately, benefit the members and their customers. While the expanded Constellations efforts are still in the discussion and planning stages, the group’s ultimate goal is to simplify the IP exchange process between vendor and integrator. Towards this end, Constellations is offering a free, one-day conference on March 31 in Santa Clara on “What keeps you up at night about buying IP?” The event will comprise presentations and panels discussing the technical and business issues of purchasing IP from an outside source. To register for the conference, please go to: http://constellations2010.eventbrite.com/

There has been a trend over the past several years in the electronics community. It has been driven by the dismal economy along with the rise of social networking. I am referring to the diminishing number of technical editors covering electronics technology.

Virtually every electronics trade journal has seen a substantial decrease in the size of their full-time editorial staff. These people are the ones, through long-term experience and a good set of contacts within the various companies and trade organizations they write about, who gave us in-depth, well balanced and well written articles on a wide range of interesting technology topics. The key term here is ‘well balanced’ – good technical editors can write without bias and cover the pluses and minuses of a cool technology, industry trend and emerging application.

Well, unfortunately, these people are fast disappearing. Taking their places are blogs and other social media venues for technology coverage – but without the constraints and guidelines of a well-run publisher. As interesting and informative as they may be, blogs are, essentially, opinion pieces. Bloggers, me included, offer opinions on various subjects and do not always present hard and fast facts or a balanced argument. This is not to say blogs are bad – good bloggers present very interesting pieces on some fascinating subjects. However, bloggers are not replacements for the traditional technical editorial staff on publications such as Chip Design, EDN, Electronics Design, EETimes and many others.

Editorial technology coverage, as we know it, is fast disappearing. To the detriment of the electronics community, it is going…going…almost gone, and that’s a real shame.

Attending the GSA Suppliers Expo and Conference earlier this month was a sobering experience. During a 9 ½-hour stint in my company’s booth, I saw firsthand how the sour economy has affected the networking that goes on at industry trade shows.

As expected, lots of people, including many ex-colleagues and acquaintances, stopped by to see how I and my company were doing and to trade stories about what has happened since the last time we had a chance to chat. This is all well and good; unfortunately, there were also several other visitors, some who I knew and a few I did not know, who stopped by to inquire about work opportunities. This is the reality of a trade show in a today’s severely down economy with many people either unemployed or underemployed.

I am sure all of us know several people in the semiconductor industry looking for work. A couple of fellows I know have been unemployed for over a year; one for 18 months. Having the analysts tell us that the industry is starting to rebound doesn’t help these people – they are out of work and have bills to pay.

The really unfortunate part of all this is that many of the jobs that have been eliminated are not coming back. As past downsizing periods have shown us, companies “thin the herd” of employees to accommodate a business downturn and then, when business picks up, they increase the workload of current employees and only partially refill the employee pool to prior levels at comparable business loads.

This is the new business climate, it is here to stay and we all have to live with it.

I recently sat in on a webinar sponsored by eg3.com on “How Designers Search – Survey Results.” The information in the webinar was gleaned from the 185 managers, engineers and programmers working in commercial or military positions out of 443 respondents to a survey sent to eg3.com’s 43,000-plus subscriber list – a small sample, but still meaningful.

The survey asked a series of questions to determine: how engineers and programmers search for information on technology, what content they seek, and what are their search strategies. I am normally skeptical of free webinars to the engineering community (since so many are thinly veiled sales or marketing pitches), but this was a pretty good one, with some expected results and a few surprises.

Not unexpected, search engines are highly regarded and used by engineers, virtually all the time. Google is King, followed by Yahoo (a distant second) and Microsoft’s Bing. Beyond search engines, other Internet-based media was a very good source of information to the engineering community, while emails and newsletters were also highly regarded.

Social media as information sources is growing slowly and, currently, appears to be greatly overhyped for this purpose. While still popular (but significantly behind search engines), trade shows and print publications are losing ground.

The survey results also gave insight into how engineers search on the Internet. I was surprised to find out that most do not give up after the first page of links, but go down as far as the third page. In fact, almost 40% “often” or “always” go as far as Page 10 on their searches.

In the “What do Designers Want” category, ‘hands-on’ items such as demos, software and evaluation kits rank very highly. On the flip side, vendor articles and webinars ranked moderately low and podcasts very low in response to a “What Information do you seek” question (the webinar response probably due to the same perception that I have that many are sales or marketing tools).

There was a lot of other useful information in the webinar, making this hour a good use of my time. For more information on future eg3.com’s marketing webinars on Search Engine Optimization (SEO), free and paid, go to www.eg3.com/technology-marketing/seo.htm.

One of the less recognized aspects of the Design Automation Conference is the Pavilion Panels program that takes place on the exhibit floor. Covering a broad range of business and technical topics, these relatively informal sessions include roundtables, presentations and other goodies throughout DAC week.

One not to be missed this year is an industry retrospective that will be given by Doug Fairbairn. One of Silicon Valley’s true visionaries, Doug has had a rich career including editor-in-chief of a ground-breaking industry publication, the old Lambda magazine; co-founder of VLSI Technology, one of the first true ASIC companies; founder of Redwood Design Automation; and much more.

Doug’s talk will provide a retrospective on major shifts in the electronics industry over the last quarter century and how they have shaped the design tools and methodologies of today and tomorrow. But wait, there’s more. After his presentation, Gary Smith and Richard Goering will join Doug to provide their perspectives on Doug’s presentation and discuss what it all means for the industry’s future.

This is a very unique opportunity to hear a semiconductor/EDA veteran who has seen and heard it all. It takes place from 10:45-11:45 Monday morning in the DAC Pavilion (Booth #1928), in the exhibit hall. If you are going to DAC, don’t pass this up.

No, I’m not talking about stargazing. This Constellations is the IP collaboration program launched by IPextreme earlier this year.

Four of the Constellations partners – CAST, IPextreme, Sidense and Sonics – are sponsoring a luncheon at DAC on Wednesday, July 29, where you can hear about “The Changing Face of the IP Industry.” Following a keynote talk by Jim Hogan, well-known semiconductor and EDA veteran, the luncheon will feature a Constellations overview followed by a panel manned by the sponsoring partners. The panelists will discuss current and evolving techniques for obtaining on-chip resources, along with some of the technologies available in third-party IP that can help you with your chip designs.

Identifying, selecting, and implementing IP is difficult. Web searches and IP portals such as ChipEstimate.com and Design & Reuse are useful for IP identification, but the expertise of the Constellations partners add another dimension for connecting IP integrators with the right IP providers.

If you would like to sign up for the Constellations luncheon, visit:
http://www.ip-extreme.com/daclunch_reg.html

In an article this week in one of the industry trade publications, an iSuppli source was quoted as saying, “The usable limit for semiconductor process technology will be reached when chip process geometries shrink to be smaller than 20 nm, to 18-nm nodes.” According to iSuppli, this will occur in 2014 when Moore’s Law will not drive volume production. This is an interesting take on the divergence of Moore’s Law and the economics of the semiconductor industry.

The technological advancements of the semiconductor industry have amazed me for as long as I have worked in it. I remember transistors with five-micron features in the early 1970s and a worry at Texas Instruments about having equipment available for volume IC production much beyond that point. During the intervening 35 years or so, various industry visionaries have predicted a “practical” limit to process node shrinkage for a variety of reasons – manufacturing capability boundaries, design limitations, and even a physics-based stopping point; I believe Carver Mead set the latter at around 10nm. Now we have another factor to consider when contemplating the silicon “wall” – economics.

iSuppli postulates that process node shrinkage won’t be limited by the ability to make devices smaller (through shrinking feature sizes). Instead, it will become too expensive for most chips to utilize a process node below 18-20nm. This is an interesting concept, but not a really surprising one. Mature process nodes are much more economical to use than leading-edge ones; the older nodes have already gone through the roughly 30% learning curve (and price reduction) per year for the first few years. And while leading-edge process development is necessary for continuing the advancement of the chip industry, most products do not need to be fabricated at 45nm and beyond to show a good profit margin and, in fact, certain chips such as analog and mixed signal devices do better at the larger process nodes.

So, do I agree with iSuppli’s analysis? Pretty much so, although the 2014 date and 18-20nm node size may be off. In addition, some new and highly innovative silicon (or other semiconductor) structure may come along and throw everything out of whack.

That’s what makes working on our industry so much fun!