Tuning into Jim

In an article this week in one of the industry trade publications, an iSuppli source was quoted as saying, “The usable limit for semiconductor process technology will be reached when chip process geometries shrink to be smaller than 20 nm, to 18-nm nodes.” According to iSuppli, this will occur in 2014 when Moore’s Law will not drive volume production. This is an interesting take on the divergence of Moore’s Law and the economics of the semiconductor industry.

The technological advancements of the semiconductor industry have amazed me for as long as I have worked in it. I remember transistors with five-micron features in the early 1970s and a worry at Texas Instruments about having equipment available for volume IC production much beyond that point. During the intervening 35 years or so, various industry visionaries have predicted a “practical” limit to process node shrinkage for a variety of reasons – manufacturing capability boundaries, design limitations, and even a physics-based stopping point; I believe Carver Mead set the latter at around 10nm. Now we have another factor to consider when contemplating the silicon “wall” – economics.

iSuppli postulates that process node shrinkage won’t be limited by the ability to make devices smaller (through shrinking feature sizes). Instead, it will become too expensive for most chips to utilize a process node below 18-20nm. This is an interesting concept, but not a really surprising one. Mature process nodes are much more economical to use than leading-edge ones; the older nodes have already gone through the roughly 30% learning curve (and price reduction) per year for the first few years. And while leading-edge process development is necessary for continuing the advancement of the chip industry, most products do not need to be fabricated at 45nm and beyond to show a good profit margin and, in fact, certain chips such as analog and mixed signal devices do better at the larger process nodes.

So, do I agree with iSuppli’s analysis? Pretty much so, although the 2014 date and 18-20nm node size may be off. In addition, some new and highly innovative silicon (or other semiconductor) structure may come along and throw everything out of whack.

That’s what makes working on our industry so much fun!

If you are like me, trying to get all the information you need to do your job can be a harrowing experience. With so many sources from which to choose, how do you know which ones are right for you to stay current? Well, a little help is on the way in the form of a DAC panel, “Tweet, Blog or News: How Do I Stay Current?”

Presented as a Pavilion Panel Wednesday afternoon on the DAC show floor, this will be more like a roundtable than a true panel, with a moderator, three participants and no slides. The panel’s goal will be to help you understand the various information sources you have available – including traditional ones such as print and online publications along with the newer blogs, portals and social media networks – and what each has to offer.

Each of the three panelists will give a position statement, followed by a group discussion on topics such as how to find your way around the various information sources, what tools are available to use these sources and what is the best way to use them. The panelists will even give some advice on how to start blogging.

There is an overabundance of things to see and do at DAC, but I would put aside the Wednesday, July 29, 4-5PM slot to sit in on this panel. The topic is interesting, timely and, who knows, you might pick up some pointers on how to make your job easier. Check out the panel details at: http://www.dac.com/events/eventdetails.aspx?id=95-106

Post-VSIA has been an interesting time for the IP industry, with work on IP qualification standards slowing to a crawl and not a lot of interesting news concerning the IP industry as a whole. Enter the Constellations Program this past week, complements of IPextreme and a handful of founding members.

Constellations aims at “leveling the playing field” for small IP vendors through a sales collaboration program between IPextreme and Constellations members, who initially include CAST, NXP, Sidense and Tiempo. Based on a lead-sharing concept, a Constellations member inputs a lead (with permission of the inquiring customer) for IP that they do not supply into a database that is shared by the other Constellations members who have IP matching the request. These other members can then follow-up on these leads through their sales departments. The follow-up is voluntary and the leads go to members without any implicit endorsement, meaning that interested members have an equal opportunity to close business based on any lead.

If a business deal is successfully closed, the company getting the IP business pays a royalty that is shared by IPextreme and the company that submitted the lead. Constellations members, who pay a small annual fee to IPextreme, also participate in co-marketing and co-promotional programs that are guided by IPextreme.

I think this is a very interesting concept and one that goes beyond IP catalogs in portals such as chipestimate.com and Design and Reuse, since Constellations members help “qualify” the match between IP inquirer and IP vendor. I look at the Constellations model as supplying a supplemental “front end” to a company’s sales force for initial business lead identification. The key to Constellations’ success will be the ability to scale up the program beyond the initial five members; I think 30-50 members would be a nice target number. If successful, Constellations will prove to be a win/win/win situation for the lead-submitting member, the member who gets business and, ultimately, the customer who finds the IP they are seeking.

To find out more about Constellations, go to: www.ip-extreme.com/partners/constellations.html

Over the past few years, I have had the opportunity to sit in on several conference and other event keynotes given by Wally Rhines, Mentor CEO and Chairman. Wally’s presentations are always very informative and entertaining – the keynote he gave at DesignCon this week was no exception. He called it, “Common Wisdom Versus Reality in the Electronics Industry.” I think of it as electronics industry myth busting.

In his talk, Wally tackled a number of popular concepts, including: the slowing adoption of new technology: the belief that in a stable EDA market there is no opportunity for change; the increasing cost of EDA tools is making them unaffordable to many; more companies are moving towards single-vendor EDA flows; and consolidation in the semiconductor industry. He then proceeded to show why each of these statements is not true, through the use of some very thought-provoking charts and graphs based on data from industry analysts and other knowledgeable sources.

While Wally’s talk focused on EDA issues, it also covered other areas of importance within the semiconductor industry, including such topics as the history over the past 25+ years of semiconductor R&D spending and the acceleration of EE headcount in recent years. These are areas to think about when evaluating the industry and considering its future during the current economic crisis.

A video of Wally’s keynote will be on the DesignCon website (http://www.designcon.com/2009) shortly. I highly recommend that everyone view it.

I just read a blog that indicated that people would rather make their electronic devices easier to use than to have their feature sets constantly expanded. Ya think?

To me, this is not an astounding revelation. For years I have been promoting ease of use as one of the top (if not the top) reason consumers buy one camera, cell phone, or DVR over another, even at a price premium. Let’s face it – most of us don’t use half the features on our digital cameras and I know that even as I take advantage of so many of the features of my iPhone, I realize that there are several I haven’t even considered. And I, for one, always read the evaluations on the Web of new products I am considering buying, especially the reviews of how easy it is to use those products.

Speaking of the iPhone, this is a prime example of a manufacturer – Apple – getting it right. When first introduced almost two years ago, the virtual keyboard, lack of “real” buttons and intuitive nature of the command hierarchy on the iPhone put other cell phone manufacturers to shame. The result now is that several of these other cell phone vendors are duplicating many of the iPhone’s features for their own products. This points out what I consider a big problem in the consumer electronics product arena – the push for product feature-set enhancement over the ability to learn and use the product quickly and easily.

The need to make products easier to learn and use transcends the consumer marketing place. A few years ago, some EDA vendors realized the value of developing and selling design tools that did not need several days of training to use and several more months of use to gain proficiency in their use. While not pervasive throughout the industry, the ease-of-use concept has gained a foothold in the EDA community, both on the development and the buyer side. Similarly, semiconductor IP vendors, at least the good ones, realize that the easier it is to implement their products in chips, the more attractive they are to IP integrators. Having a good service component to your company also is very valuable to companies selling products such as EDA tools and IP.

Vendors of consumer electronic products need to change their way of thinking from “I need more whiz-bang features than my competitor” to “my product needs to be easier to use compared to that of the competition.” This is particularly true as the consumer electronics marketplace expands globally and includes a broader range of potential customers with a more diverse set of educational backgrounds. Right now, learning to use your new MP3 player makes setting the clock on the old VHS recorder seem like child’s play. No, wait – kids could always do a better job at that than most adults.

Unless you have been living on a deserted island in the middle of the Pacific the past few months, you are well aware of the serious financial straits our country is in right now. The latest business to come under the microscope is the automotive industry, particularly the Big Three (Chrysler, General Motors and Ford). Why am I not surprised?

For years, the U.S. automotive giants have been blind to what is needed to stay competitive in a global industry, particularly with respect to the need for more fuel-efficient vehicles. By continuously pumping lobbying money into Congress, they have been able to effectively slow down the inclusion of technological advancements that have been available to increase mpg. As a result, U.S. automakers’ market share has been steadily dropping over the years. This is not a surprise to anyone; what does open my eyes, however, is the discrepancy in compensation between the U.S. Big Three and Japan’s Big Three (Honda, Nissan and Toyota).

According to Mark Perry, University of Michigan professor of economics, average hourly compensation for the U.S. Big Three is $72.31. For Japan’s Big Three, it is $44.20. Cost of living aside, this is a huge difference in compensation (wages, medical benefits, vacation, etc.) and is an example of why the U.S. auto industry is in such dire straits (a shrinking market and over-bloated compensation is a recipe for failure). Many of these highly compensated U.S. auto workers will be out of work in the not-too-distant future, as well as many employees of component and subsystem suppliers to the U.S. car makers.

Throwing more money into the automakers coffers is not the answer without guaranteed changes within the industry. We in the semiconductor industry are an integral part of automotive development, with semiconductor content in cars rising each year. We supply technology that can assist car makers in realizing more efficient vehicles for less money. However, more and better silicon isn’t the only answer. The serious problems in the U.S. automobile business have been years in the making and combine the greed and, yes, stupidity of U.S. auto industry management and workers along with, of course, the federal government. It’s going to take a lot of serious thought and compromise to right the U.S. automotive business and there are no guarantees that this ship will still not go down with all aboard despite rescue efforts.

A few days ago a friend emailed me the link to a YouTube video (http://www.youtube.com/watch?v=W1czBcnX1Ww) from a company called Boston Dynamics. The video was of BigDog, a radio-controlled, quadruped robot carrying a 300-plus pound payload over uneven terrain, snow and ice, moving and staying upright even when kicked by a human. I don’t often get excited about videos (heaven knows there are enough of them around on every subject imaginable), but BigDog’s is absolutely fascinating. It brought to mind an area of engineering that many of us in the semiconductor field don’t hear or think enough about – robotics – or, even more specifically, mechatronics.

By combining aspects of microelectronics, mechanical engineering and control systems, mechatronics successfully encompasses multiple engineering disciplines to develop products that come into our lives in many diverse areas. Some of the more interesting examples are the Segway personal transportation system, Roomba automated vacuum cleaner and bomb-sniffing robots used by police.

Too often, we electronics types are too involved with “our�? engineering world, that of the transistor and its non-silicon support subsystems, such as batteries (for power) and antennas (for wireless data transmitting and receiving). Besides the occasional motor control, sensor conditioning and camera manipulation, for the most part chip designers are involved with what happens on the silicon and meeting the specs required to work in a particular (electronics) system. Systems knowledge is usually confined to the electronics system.

BigDog is a great example of a well-engineered, multi-discipline system. The future growth of the semiconductor industry will come as chip engineering continues to merge with mechanics, fluidics, biology and other scientific field of study. We should all watch the BigDog video and start thinking outside of the silicon box.

It was a busy week in Silicon Valley recently with two interesting and free one-day events taking place two days apart, the Common Platform Tech Forum and the GSA Expo. These types of events, financed by sponsorships and exhibitors, allow attendees to obtain a lot of information about industry segments and, often, trends in a relatively short time. Having attended both, I came to a conclusion – there are some interesting developments taking place in the options you have available for chip processing.

The birth and growth of the independent semiconductor foundry business several years ago marked a change in how chip developers could have their designs processed. Up until then, the rapidly rising cost of a silicon processing facility meant that only the largest semiconductor companies could afford to have wafer fabs dedicated to leading-edge silicon processes. By utilizing economies of scale achieved from processing chips from several companies, pure-play foundries fueled the growth of the fabless semiconductor industry and allowed even very small (and often highly innovative) chip companies to bring their products to market.

Besides taking advantage of volume wafer processing, successful foundries were also able to achieve business clout and bargaining status by developing partnerships with EDA, IP and design services organizations. This permitted the foundries to take on the role of “one-stop shops�? for many of their customers. In fact, IP and EDA relationships often defined the value-added features of one foundry over another.

The Common Platform consortium represents, to me, further evolution in semiconductor process availability. Developing silicon processes that can go to multiple foundries, in this case IBM, Chartered and Samsung, gives customers flexibility in where they manufacture chips and also solves the problem for many companies of having a second wafer processing source. But the Consortium has gone beyond multiple foundry availability. With a Joint Development Alliance that includes Freescale Semiconductor, Infineon, ST Microelectronics and Toshiba, the Consortium has added valuable knowledge and experience in advanced chip design, which they use in the development of next-generation process nodes, currently targeted to 32nm and 28nm. The Alliance is what gives the Common Platform Consortium an edge over pure-play foundries such as TSMC and UMC in process node development.

The GSA Expo, a broad gathering of EDA vendors, foundries, IP developers and chip companies, offers a large group of exhibitors along with several keynotes and technical sessions covering a wide range of semiconductor topics. As in past years, I find the GSA Expo a good place to discuss industry trends and issues with colleagues, such as the pluses and minuses of pure-play foundries vs. process-platform consortiums.

I think the Common Platform model is a good one and will no doubt lead to the formation of other successful process development consortiums down the road. If nothing else, these cooperative efforts in process node development will put pressure on the pure-play foundries to stay on their toes and not get complacent about their R&D efforts.

I read in my local newspaper earlier this week that Carnegie-Mellon professor Randy Pausch died at age 47 of pancreatic cancer. Some of you may have heard of Randy late last year for his “Last Lecture�? at CMU on “Achieving your Childhood Dreams,” which has had almost five million views on YouTube (http://youtube.com/watch?v=ji5_MqicxSo&feature=related). Randy, a husband and father of three small children, knew about his terminal condition in 2006 and died wanting no sympathy (his own words) because he had been able to achieve many of the seemingly lofty goals he set before himself as a child. In other words, he had taken the proper perspective of work vs. “life outside of work�? and been happy with his priorities.

Having lived and worked in the Bay Area for over 30 years, I have seen many colleagues and friends with a “Silicon Valley�? mentality – working long hours, including weekends, and feeling a need to be connected 24/7. To me, this is fine so long as it doesn’t interfere with an enjoyable lifestyle and fulfilling relationships with family and friends. I love what I do (currently marketing for a memory IP provider) and I too am immersed in a busy work schedule, but I also see the need for and importance of reasonable R&R, doing things I enjoy doing.

The many orchards and hot houses that populated Silicon Valley when I arrived here in 1974 are long gone, replaced by silicon factories and design facilities, along with the housing needed to support the people working there. But there are still roses to smell and opportunities to live your childhood dreams in what is one of the most lovely and opportunity-filled regions in our country. For those of you who live here, take time to enjoy your stay along with getting the satisfaction you do from your work. Randy had the right idea – you don’t get a second chance so make the most of the first one.

And take time to see and hear Randy’s Last Lecture – you won’t be disappointed.

At the Design Automation Conference earlier this month, I participated in a breakfast roundtable to discuss the ease (or lack thereof) of integrating third-party silicon IP into a design. Details on the roundtable were discussed in my last blog (June 4), but my co-participants – Steve Leibson of Tensilica, Adam Traidman of ChipEstimate.com and Navraj Nandra of Synopsys – and I were fairly consistent in our view that if will be very difficult to make third-party IP integration a turnkey operation.

At this time there appear to be three obstacles to “easy�? IP implementation on a chip: lack of standardization about what constitutes quality IP and a “good�? IP supplier; the fact that every reuse of a piece of IP constitutes putting the IP into a different system environment on the chip, each with its own unique interface and timing considerations; and IP and overall chip complexity continue to increase as process nodes shrink. Furthermore, when you consider analog/mixed-signal IP, the IP integration task becomes even more daunting.

The first barrier to turnkey IP integration, lack of standardization, was addressed for a time by the now dissolved VSIA. While the Alliance made progress in IP qualification standardization, no one as yet has successfully continued this development although the IEEE, which picked up the VSIA work, should show some further improvement in qualification standards down the road. What are also needed are customers who demand a global quality IP standard for selecting IP and IP vendors; right now, too many companies rely on internal means of gauging quality

Successful IP reuse will continue to be a problem due to system-level issues when implementing IP in an SoC. As much as we would like to think that we can treat IP as a separate entity, there are too many interactions on the chip to do so – each SoC represents a different set of requirements for IP integration and verification.

Finally, as IP and overall chip complexity continues to grow, there is an increasing need for better “system-like�? tools that operate on an SoC and its blocks. Such tools will eventually be available for IP integration, but what is available currently is not adequate.

So, yes, my short-term view of turnkey IP integration is a negative one. An IP supplier must become more of a partner to the IP integrator and not just a supplier of IP. The suppliers, along with possible third-party “IP integration facilitators,�? similar to design houses but focusing on IP implementation, must provide a higher level of service to the integrators. In other words, look at the absence of a turnkey IP integration methodology as an opportunity for more engineering jobs in the semiconductor industry.