Mr. Jaeger joined Synplicity in 2007 after spending more than 10 years in various marketing positions at IKOS Systems and later Mentor Graphics. He started his career as a hardware designer and has more than 20 years of experience in marketing and product marketing of design and verification solutions for ASICs and FPGAs. He studied electrical engineering at the Fachhochschule of Kaiserslautern in Germany and computer science at the University of Hagen in Germany.
Fahrvergnügen
High-performance ASIC Verification
About
Mr. Jaeger joined Synplicity in 2007 after spending more than 10 years in various marketing positions at IKOS Systems and later Mentor Graphics. He started his career as a hardware designer and has more than 20 years of experience in marketing and product marketing of design and verification solutions for ASICs and FPGAs. He studied electrical engineering at the Fachhochschule of Kaiserslautern in Germany and computer science at the University of Hagen in Germany.