The German word Fahrvergnügen directly translated means “the joy of driving“, and anybody who has ever driven a performance car on the German Autobahn knows what I mean, they know that exhilarating feeling, and the joy, das Vergnügen to do so. On the other hand, driving a car can sometimes be a painful dread, like being stuck in traffic that causes you to be late for a critical appointment.
Which brings us to the real topic of this blog: ASIC and SoC verification, more specifically hardware-assisted verification and FPGA prototyping. Verification always was and still is the most time consuming task in any ASIC and SoC design project. And it is often also the most daunting and sometimes frustrating task; it can feel like sitting in a traffic jam and not being able to reach your destination in time, which is not fun – no Vergnügen!
So how do we make verification more fun? Well, what makes driving on the Autobahn fun? The obvious answer is: driving a high-performance car, which for verification translates into using a high-performance verification methodology. And although all hardware-assisted verification methodologies offer superior performance over traditional software-only verification tools, one clearly stands out and surpasses all others: FPGA prototyping! Just imagine how much Vergnügen it is to get your verification results in a few seconds, instead of waiting for them for days or even weeks. Think about how good it will feel to get from point A to point B in record time – getting your verification done on time.
But the similarities don’t end here. Anybody can drive on the Autobahn, there are no access fees, no tolls – having Fahrvergnügen on the Autobahn is affordable. Similarly FPGA prototyping is affordable for everybody doing ASIC and SoC designs. There are no prohibitively high costs associated with it, like there are for emulation for example.
But there are also challenges, most noticeably in the areas of ease-of-use and debugging capabilities that need to be addressed. With this blog, I hope to stimulate discussion and dialog around all aspects of ASIC and SoC verification. I am looking forward to hearing from you, to get your input and your feedback as we navigate this high-speed road together.