This is the November 2007 edition of the IP Designer & Integrator. We complement Chip Design magazine by providing semiconductor IP news, opinions, and articles. There are subscribe and unsubscribe options at the end of the page.

This Month's Table of Contents:

1. Editor's Note
   
2. Choosing the Right AMBA On-Chip Bus IP for Consumer Product Design
   
3. Algorithmic Synthesis and IP: the Perfect Match
   
4. Small Processor Core Combines with ESL Technology
   
5. Working-First-Silicon for PCIe PHY with Leading-Edge DFT
   
6. Collaboration Makes Processor Core Available for ASIC Designs
   
7. SATA II IP Fits Storage and Connectivity Markets
   
8. Multimedia IP Cores Define Digital Video and Audio Applications
   
9. Fully-Programmable Multi-Processor Solution for Full HD Video
   
10. In-Depth Coverage Links
    
• "Achieving Success in an Increasingly Complex Design Environment"
  
• "Soft IP Actually Does Exist for the Analog ASIC"
11. Book Review
• The Semiconductor IP Handbook
12. Happenings

Platinum Sponsor: Synopsys
Gold Sponsor: Lightspeed

1. Editor's Note

In this issue Meni Jayaswal of Synopsys shares tips for effectively using AMBA IP. Make your reservation now for a short trip to success in "Choosing the Right AMBA On-Chip Bus IP for Consumer Product Design." Then clear your calendar for a meeting with Simon Napper, President of Synfora. He offers a new approach in "Algorithmic Synthesis and IP: the Perfect Match." These treats are followed by the solid staples of timely information in our news briefs and regular features.

2. Viewpoint – Exclusive

Choosing the Right AMBA On-Chip Bus IP for Consumer Product Design

By Meni Jayaswal, Staff CAE, Synopsys

To ensure that PDAs today can double as a digital camera and the digital camera can in turn handle video streams, these devices need an on-chip bus that runs at a high frequency and delivers high bandwidth—with some qualifications. Those qualifications include the IP's silicon area and overall cost as well as complexity issues.

Analyzing these factors isn't overly complex when choosing between the AMBA 2 and AMBA 3 AXI protocols. By comparing performance, bandwidth, and area requirements, users can easily make the right architecture choice early in the design cycle. Applying this information to two real-world examples—a PDA and a digital camera design. A quick analysis of performance, bandwidth and area can help clarify which protocol is right for your application needs. Full Story »

Lightspeed Logic's mask reconfigurable foundation IP enables flexibility, rapid time-to-market, reduced development expense and increased deep-submicron yield.

Lightspeed

3. Viewpoint – Exclusive

Algorithmic Synthesis and IP: the Perfect Match

By Simon Napper, President and CEO of Synfora

In the fast-evolving world of consumer electronics, the need to conquer increasing complexity grows daily. Better, faster and cheaper products necessarily demand ever more complex ICs, which must be designed for the same cost, in the same or less time. But this situation cannot sustain itself for much longer, because existing flows and methods have already been stretched to the limits of their capabilities over the last decade. Clearly, a change of approach is needed.

The solution is abstraction. Abstraction has been proven many times, but so far the industry has had limited success in moving to the next level. This failure can be attributed partly to a designer's natural resistance to change, and partly to a lack of any decisive "killer" application offered by those in the business of providing solutions. At last, however, both sides are coming together to build a bridge to the future. Full Story »

4. News: Small Processor Core Combines with ESL Technology

CoWare, Inc. and Tensilica, Inc. have integrated Tensilica's Diamond Standard 106Micro, a small licensable 32-bit processor core, with CoWare Platform Architect to create an ESL 2.0 solution for platform architecture design, platform verification and software development. The core measures less than 0.1 mm2 in 65-nanometer GP process technology while using just 0.029 mW/MHz of power. It is particularly attractive to designers upgrading from 8- and 16-bit controllers to a 32-bit processor and C-level programming flexibility. The design platform is a SystemC-based graphical environment for capturing the entire product platform and the dash board for initiating the platform analysis functions. Applications range from peripheral and interface design to networking, automotive, industrial control, and consumer devices.
CoWare >> www.coware.com
Tensilica >> www.tensilica.com

5. News: Working-First-Silicon for PCIe PHY with Leading-Edge DFT

Phylinks, Inc. has delivered working-first-silicon of its PHY-820 PCIe PHY at the .13u process technology node. The PHY is designed with a robust design-for-test (DFT) architecture, small footprint, and low power consumption. It is the debut product in an upcoming lineup of high-speed mixed-signal IP with extensive DFT capabilities. The company has teamed with ASIC Architect, Inc. to provide SoC designers with a complete PCIe solution that includes PCIe PHY, link controller, and sample software. Avery Design Systems Verification IP was used to verify the PHY-820 together with ASIC Architect controller, providing assurance for designers who need reliable interoperability to meet tight product deadlines.
Phylinks, Inc. >> www.phylinks.com

6. News: Collaboration Makes Processor Core Available for ASIC Designs

Altera's popular Nios II processor core will be available for licensing through Synopsys' DesignWare Star IP Program. Expanding on existing FPGA and HardCopy structured ASIC product deployment options, this new offering enables users to migrate their designs to standard cell ASICs. The processor core is the most widely used FPGA-based processor, with more than 5,000 electronics manufacturers -- including the world's top electronics OEMs -- in the customer base. Star IP program provides designers access to high-performance, high-value processor and DSP cores developed by leading providers. Designers will be able to use the core in the foundry and process technology of their choice.
Altera >> www.altera.com
Synopsys >> www.synopsys.com

7. News: SATA II IP Fits Storage and Connectivity Markets

MoSys, Inc. has made two new Serial ATA (SATA) Physical Layer (PHY) IPs: SATA GEN II PHY IP and GEN I PHY IP. The first is compliant with Serial ATA II Electrical Specification Revision 2.5 and is backward compatible to the widely deployed Gen I (1.5GbS) Serial ATA standard. Key functions include the use of Out-Of-Band Signaling (OOB) protocol for initializing the SATA Interface to execute a pre-defined speed negotiation function. The second, Serial ATA Gen I PHY design, is compliant with the requirements stated in the Serial ATA standard, rev 1.0a. The IP is designed in 180nm and 130nm General (G) processes and can be readily ported to 65nm and 45nm technologies.
MoSys >> www.mosys.com

8. News: Multimedia IP Cores Define Digital Video and Audio Applications

TranSwitch Corporation has new HDMI 1.3 IP cores for high performance digital video and audio applications. The HD-PXL-1.3 transmitter and receiver IP cores will be sampleable in 90 nm CMOS technology. The cores are available in two versions each. The first version meets all the current HD (High Definition) standards up to 2.25 Gbps. The second version supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps. The transmitter IP core and the DSP-based receiver IP core can run at aggregated speeds of up to 10.5 Gbps and support color depth of up to 16 bits.
TranSwitch >> www.transwitch.com

9. International News: Fully-Programmable Multi-Processor Solution for Full HD Video

Silicon Hive B.V. of the Netherlands has announced its VSP 2500 Video Signal Processing solution for Full High Definition (HD) video codecs. It is a multi-processor system that scales with unique tile architecture. By adding or removing tiles, SoC platform owners can address various operating points in terms of area, power, and performance. A two-tile system can be programmed in software to support 1080p 30fps H.264 baseline Level 4 decoding using a 225MHz Clock. Adding more tiles extends functionality by addressing encoding and transcoding applications, and even enables further video processing such as scaling, frame-rate conversion, and noise reduction to be realized. Other standards are programmable in software as well.
Silicon Hive B.V. >> www.siliconhive.com

10. In-Depth Coverage Links

Design reuse isn't just a great idea, it's crucial. In this article, Kalar Rajendiran reflects on the role that the Value Chain Producer can take in making sure IP fits smoothly into new ideas. Ride the changing semiconductor ecosystem in "Achieving Success in an Increasingly Complex Design Environment."
Featured Story >>
http://www.chipdesignmag.com/display.php?articleId=1255&issueId=23

Sometimes a clean digital approach is an unaffordable luxury. Real life is down, dirty and analog! Reid Wender knows his away around Mixed Signal designs. The truth is out there, and it's not all ones and zeroes. Speed your search with "Soft IP Actually Does Exist for the Analog ASIC."
Featured Story >>
http://www.chipdesignmag.com/idesign/index.php

11. Book Review

The Semiconductor IP Handbook
By Steve Deeley
ISBN-10: 0387289119
ISBN-13: 978-0387289113
Publisher: Springer

The plan is to address the commercial and technical pitfalls that surround IP development and use. This book is based on real-life examples and covers licensing agreements to coding standards and business models. The intent of the author is to show how to avoid many common problems that have affected projects in the past. This should be an interesting book for our readers, yet I have not been able to locate a copy, just conflicting publication dates. Here's one of the stores that assumes it's on hand. Some state it won't be out until after the first of the year. Let me know if you find it.
http://www.amazon.com/Semiconductor-IP-Handbook-Steve-Deeley/dp/0387289119

12. Happenings – Conferences

IP Based Electronic System Conference (IP2007)
December 5-6, 2007
World Trade Center, Grenoble, France
www.us.design-reuse.com/ip07

SEMICON Japan 2007
December 5-7, 2007
Makuhari Messe, Chiba, Japan
www.semiconjapan.semi.org/SCJAPAN2007-EN/Visitors/index.htm

2007 IEEE International Electron Devices Meeting
December 10-12, 2007
Hilton Washington, Washington, DC
www.his.com/~iedm

International Conf, on Field-Programmable Technology 2007
December 12-14, 2007
The Kitakyushu International Conference Center,
Kokurakita, Kitakyushu, JAPAN
www.kameyama.ecei.tohoku.ac.jp/icfpt07

International Conference on Microelectronics (ICM 2007)
December 29-31, 2007
Nile Hilton, Cairo, Egypt
www.ieee-icm.com

2008 International CES
January 7-10, 2008
Las Vegas Convention Center, Las Vegas, Nevada
www.cesweb.org

International Solid-State Circuits Conference 2008
February 3-7, 2008
San Francisco Marriott Hotel, San Francisco, California
www.isscc.org/isscc/index.htm

DesignCon 2008
February 5-6, 2008
Santa Clara Convention Center, Santa Clara, California
www.designcon.com/2008

DVCon 2008
February 19-21, 2007
Doubletree Hotel, San Jose, California
http://www.dvcon.org/

FPGA 2008
February 24-26, 2008
Monterey Beach Resort, Monterey, California
www.ece.wisc.edu/~kati/fpga2008

International Symposium on Quality Electronic Design (ISQED'08)
March 17-19, 2008
DoubleTree Hotel, San Jose, CA
www.isqed.org

IP DESIGNER & INTEGRATOR e-NEWSLETTER CONTACTS

Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com

Advertising/Sponsorship Opportunities: Karen Popp,
kpopp@extensionmedia.com

Read past issues of Chip Designer, FPGA Developer, IP Designer & Integrator and Wireless Chip Designer: www.chipdesignmag.com/enewsletters

To subscribe, or change your profile, visit:
www.chipdesignmag.com/subscribe

Visit Chip Design:
www.chipdesignmag.com

Contact Us | Sponsor this Newsletter | Subscribe | Visit Chip Design

Copyright © 2007 Extension Media, Inc. All rights reserved.