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Welcome to the June IP Designer & Integrator. Our task is to complement Chip Design magazine by providing semiconductor IP news, opinions, and articles. There are subscribe and unsubscribe options at the end of the page.
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IP Talks! is your DAC resource for all things IP
Meet with and hear from the world’s leading IP suppliers and foundries. Don’t miss your chance to experience IP Talks! live in ChipEstimate.com booth 1100. Participants will be entered to win one of several 8GB HD video recorders.
Listening to the surf below my cliff-side motel, I have a chance to reflect on what an exciting industry we have to work in. This heavy thinking is simply a product of the Internet being down and the night clerk not wanting to climb into the attic to reset the server. Nothing like a blank screen to force thought, if only about how much I take for granted, and how fragile the everyday really is. We’re walking on a mile-high crust of chips, watching technological change flow out of silicon volcanoes with intermittent techno-explosions. It’s raining cell phones that are much smarter than I am, and tomorrow’s toaster ovens and traffic lights will make them look dumb.
Yet it all depends on what has come before. Design software and hardware depends on distilled experience, always racing to explain the present let alone plan the future. We depend on rules that may or may not last through the day. Which makes keeping up with growing, changing concerns like IP Metrics that much more important. In this issue Michel Tabusse, CEO of Satin IP Technologies in Montpellier, France, looks at how difficult IP and SOCs really are to design and asks “How Will the IEEE’s Emerging QIP Standard Contribute to IP Design Quality Closure?” Next, Sanjay Churiwala and Sapan Garg of Atrenta, and Chirag Gupta and Paresh Joshi of Texas Instruments, continue their analysis of Clock Domain Challenges in “Verification of Clock Domain Crossing in SoCs: Part Two—SoC Characteristics.” Then step into our DAC Spotlight and take a plunge into the world of IP in our news briefs and regular features. Meanwhile, the connection is back, but so is the sun; I’m closing the laptop and heading down to the beach.
To see our additional newsletters please visit: www.chipdesignmag.com/enewsletters/
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Intellectual property (IP) and system-on-chip (SoC) designers make daily use of electronic design automation (EDA) flows that are typically sophisticated, heterogeneous and expensive. This extensive tool suite, however, is still often not enough to satisfy the need for high quality / low risk implementation, while remaining within very tight schedules.
IP and SoCs are objects extremely complex to design, not only for technological reasons, but also (and primarily?) for design management reasons. Take a typical SoC design project of a 100+ man/year size, with teams involved from different continents. Dozens of IP blocks are being designed and verified at the same time as they are assembled in the chip. The embedded software is also written concurrently, with dependencies on the hardware architecture that is not yet finalized. The EDA tools involved in every design task generate megabytes of information every day, which ideally should be carefully scrutinized.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3406
By Sanjay Churiwala and Sapan Garg of Atrenta, and Chirag Gupta and Paresh Joshi of Texas Instruments
SoC Characteristics - CDC Verification Tool Features
There are many characteristics of an SoC design which a CDC verification tool should be able to handle well. (For the first part of this article, please see our May issue http://www.chipdesignmag.com/ipdesigner/2009/05/index.html
#Section_3. The final section is scheduled for our July issue.--Editor)
Mixed Language
These days, SoCs are “assembled” using IPs obtained from various sources. Considering that IPs are coming in from various sources, these IPs may be expressed in different languages, e.g., Verilog or VHDL. And, sometimes, even different flavors of the same language, e.g., Verilog95, V2K, System Verilog, etc.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3407
Jul 26–Jul 31, 2009
San Francisco, California
Moscone Center
The world’s premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, plus the NEW User Track presentations. The exhibition includes leading EDA, silicon and IP providers.
www.dac.comMoSys, Inc. has acquired substantially all of the assets and business of privately held Prism Circuits, Inc. The acquisition will expand MoSys’ product portfolio with the addition of highly valued and differentiated IP, accelerate growth and synergy in the networking and communications markets, and add a world-class team of engineers, including a highly talented, cost-efficient engineering design center in India. Prism Circuits specializes in silicon-proven, low-power, serial interface IP cores (SerDes) with data rates running at 10 gigabits per second and above, and IP cores for DDR 3 and DDR 2 parallel interfaces. Under the terms of the agreement, MoSys paid approximately $13.5 million at the closing, and potentially will pay an additional earn-out amount of up to $6.5 million subject to the attainment of specified milestones.
Prism Circuits, Inc. >> www.prismcircuits.com
MoSys, Inc. >> www.mosys.com
SEMICON West is the must-attend event of the year! See the latest products and technologies for high-tech manufacturing. Meet the people moving electronics innovation. Explore developments in 3D IC design and TSV packaging. Discover opportunities in MEMS, flexible and printed electronics, solid state lighting, and nanoelectronics at the new Extreme Electronics. Find solutions to increase productivity, improve performance, and advance product development.Check out the Infinite Possibilities July 14-16, 2009, Moscone Center, San Francisco, CA.
www.semiconwest.orgCAST Inc. has released a new Basic Video Deinterlacer IP core. The new core converts incoming interlaced video to progressive video format for further processing or display. It accepts an industry-standard 8-bit ITU-R BT.656 video stream for wide compatibility, and its lean processing means it requires little ASIC or FPGA area and causes practically no video transmission delay. The Basic Video Deinterlacer core works standalone in a variety of applications, and will provide integrated support for CAST's upcoming revised H.264 1080p Video Encoder IP core.
CAST Inc.>> www.cast-inc.com
The boards of Accellera and The SPIRIT Consortium have agreed to a merger of the two entities. The merged organization will be called Accellera and The SPIRIT Consortium name will continue to be associated with the organization's ongoing IP standardization efforts. The merged organizations will work towards a greater cooperation with other standardization groups in the industry. The two organizations currently have eight standardization subcommittees operating. These standards include: SystemRDL (Register Description Language), IPtagging, Interface Technical Committee (ITC), Open Verification Library (OVL), Unified Coverage Interoperability (UCI), Verilog Analog/Mixed Signal (AMS), Verification IP (VIP) and IP-XACT. Further details of the merger will be announced at the Design Automation Conference (DAC) in San Francisco, the week of July 27, 2009.
The SPIRIT Consortium >> www.spiritconsortium.org
Accellera >> www.accellera.org
eASIC Corporation and IPextreme are making Freescale’s 32-bit V1 and V2 ColdFire processor cores available for fast turnaround Nextreme NEW ASICs. This provides a low-cost entry point for creating customized ColdFire-based applications within consumer, medical, automotive, and industrial markets. The companies claim almost three times greater performance of comparable implementations in low-cost FPGAs, making the ASICs a price/performance alternative to both FPGA implementations and standard cell ASIC implementations. The 32-bit RISC V1 and V2 ColdFire processors are backed by a complete ecosystem of development tools, software stacks, and drivers from Freescale and other leading providers such as GNU, Green Hills Software, Wind River Systems, Accelerated Technology / Mentor Graphics, and many others.
eASIC >> www.eASIC.com
IPextreme >> www.ip-extreme.com
Geo Semiconductor Inc. “GEO” announced its formation and acquisition of major IC business lines and key elements of the IP portfolio of Silicon Optix Inc., including the Realta and the Geo ICs. GEO was founded by Paul Russo, Chairman and CEO, who formerly served as founder and CEO of Silicon Optix, Inc. and of Genesis Microchip. GEO is focused on providing the next-generation of video processing for HD and beyond by transitioning its award winning and branded (HQV – Powered by Teranex) video algorithm execution to a software platform, allowing customers to selectively integrate their own IP for product differentiation (Digital Video 2.0 – TM).
Geo Semiconductor >> www.geosemi.com
Gennum Corporation announced that its Snowbush IP group has developed the industry's first available integrated PCI Express 3.0 (Gen 3) PHY and Controller IP solution. The new IP is architected for low power and area on both the PHY and Data Link layer, and features low power consumption from a proprietary 5-tap Decision Feedback Equalization (DFE) and H-bridge transmit driver. The PHY silicon footprint is small and includes the I/Os, ESD structures, and PCS Layer, in 1-, 2-, 3-, and 4-lane configurations to reduce silicon cost. Each lane of the PHY can be configured to operate in Gen 1, Gen 2, or Gen 3 mode. Multiple 4-lane PHYs can be configured as x8, x16, x32, and greater links.
Gennum Snowbush IP group >> www.snowbush.com
Dr. Jeannette M. Wing, assistant director of the National Science Foundation (NSF), will speak during the IEEE Council on Electronic Design Automation (CEDA lunch at the 46th Design Automation Conference. Her talk is titled, “Frontiers in Research and Education in Computing: A View from the NSF.” The lunch, open to all DAC attendees on a first-come, first-served basis, will be held Tuesday, July 28, from noon-2 p.m. in Room #303-305 at the Moscone Center in San Francisco.
Dr. Wing is assistant director of NSF Computer and Information Science and Engineering Directorate (CISE), an organization that funds 84% of all academic computer science research in the United States. As part of her talk, Dr. Wing will describe the effectiveness of NSF’s investments in computing, with a Fiscal Year 2009 budget of $574 million. She will detail CISE’s research and education programs, including cyber-enabled discovery and innovation, cyber-physical systems, data-intensive computing, network science and engineering, socially intelligent computing, and trustworthy computing.
For more details, visit the CEDA website:www.c-eda.org
Several years ago, DFM challenges gave rise to a new class of “silicon-aware” IP. But as design becomes increasingly complex, the focus is shifting to the robustness of functional verification in the IP. As Kamalesh Ruparel explains, a new class of IP solutions, which are categorized as “high-speed interfaces,” meets with additional technical challenges at the package, board, and system levels. This trend has spawned its own requirement to create IP that is “system-aware.” Check your awareness with his “Low-Risk, High-Speed Interface IP Meets Stricter Performance and Functional Requirements.”
Featured Story >>http://www.chipdesignmag.com/display.php?articleId=2711&issueId=31
For those few who aren’t already avid readers of our sister publication, the Chip Designer newsletter, I wanted to highlight Raghavan Menon’s recent article, “IP Metrics Article: Selecting IP in a Complex Design Environment.” It’s right on this month’s topic, and right on the money for an analysis of how to pick the right IP for your project.
Featured Story >> http://www.chipdesignmag.com/display.php?articleId=3379
International Symposium on Rapid System Prototyping
Paris, France
June 23-26, 2009
http://www.rsp-workshop.org/
International Symposium on Rapid System Prototyping
Paris, France
June 23–26, 2009
http://www.rsp–workshop.org/
IEEE International Conference on Application–specific Systems, Architectures and Processors
Radisson Hotel Boston, Boston, MA
July 7–9, 2009
http://www.asap–conference.org/
SEMICON West 2009
Moscone Center, San Francisco, CA
July 14–16, 2009
http://www.semiconwest.org/
ASQED 2009 (Asia Symposium on Quality Electronic Design)
KL, Malaysia
July 15–16, 2009
http://www.isqed–asia.org/
SAMOS IX: International Symposium on Systems, Architectures, Modeling and Simulation
Samos, Greece
July 20–23, 2009
http://samos.et.tudelft.nl/samos_ix/
IWLS 2009 (International Workshop on Logic & Synthesis)
Cadence Research Laboratories,
Berkeley, California
July 24–26, 2009
(Co–located with DAC).
http://www.iwls.org/
System Level Interconnect Prediction 2009
Moscone Center, San Francisco, CA
July 26–27, 2009
(Co–located with DAC)
http://sliponline.org/
IEEE Symposium on Application Specific Processors, SASP 2009
San Francisco, California
July 27–28, 2009
(Co–located with DAC)
http://www.sasp–conference.org/
46th Design Automation Conference (DAC)
Moscone Center, San Francisco, CA
July 26–31, 2009
http://www.dac.com
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009)
Cancun, Mexico
August 2–5, 2009
http://www–elec.inaoep.mx/mwscas2009/
Signal and Image Processing (SIP 2009)
Honolulu, HI
August 17–19, 2009
http://www.iasted.org/conferences/home–654.html
Euromicro Conference on Digital System Design
Patras, Greece
August 27–29, 2009
http://www.iuma.ulpgc.es/dsd09/
International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES' 2009)
Vancouver, Canada
August 29 – 31, 2009,
http://embedded.cs.ccu.edu.tw/WoRMES2009/
(held conjunction with The IEEE/IFIP International Conference on Embedded and Ubiquitous Computing)
International Conference on Field Programmable Logic and Applications
Prague, Czech Republic
August 31 to September 2, 2009
http://fpl2009.org/index.php
SBCCI2009, Symposium on Integrated Circuits and Systems Design
Piramide Natal Resort and Convention, Natal, Brazil
August 31 to September 3, 2009
http://www.lasic.ufrn.br/chiponthedunes2009/sbcci/
PATMOS 2009
Delft, The Netherlands
September 9-11, 2009
http://kobalt.et.tudelft.nl/patmos09/home.general.html
22nd IEEE International SOC Conference
Wellington Park Hotel, Belfast, Northern Ireland, UK
September 9-11, 2009
http://www.ieee-socc.org/
2009 Custom Integrated Circuits Conference
DoubleTree Hotel, San Jose, CA
September 13-16, 2009
http://www.ieee-cicc.org/
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22–24, 2009
http://www.intel.com/IDF/
2009 CMOS Emerging Technologies Workshop
Metropolitan Hotel, Vancouver, BC, Canada
September 23-25, 2009
http://www.cmoset.com/2009_Vancouver_Workshop.html
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22-24, 2009
http://www.intel.com/IDF/
2009 CMOS Emerging Technologies Workshop
Metropolitan Hotel, Vancouver, BC, Canada
September 23-25, 2009
http://www.cmoset.com/2009_Vancouver_Workshop.html
International Symposium on System-on-Chip 2009
Tampere, Finland
October 5-7, 2009
http://soc.cs.tut.fi/2009/index.php
IEEE Workshop on Signal Processing Systems (SiPS 2009)
Tampere Hall, Tampere, Finland
October 7-9 2009
http://www.sips09.org/
ARM Developers’ Conference 2009
Santa Clara Convention Center, Santa Clara, CA
October 21-23, 2009
http://www.rtcgroup.com/arm/2008/
IP–Embedded Systems Conference 2009
Grenoble, France
December 1–3, 2009
http://www.design–reuse.com/ipesc09/
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
Read past issues of Chip Designer, FPGA Developer, IP Designer & Integrator and Wireless Chip Designer: http://www.chipdesignmag.com/enewsletters/
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