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Welcome to the May IP Designer & Integrator. Our task is to complement Chip Design magazine by providing semiconductor IP news, opinions, and articles. There are subscribe and unsubscribe options at the end of the page.
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As I write this there are some good signs on the far horizon—and my 401k is looking a tiny bit less devastated. But in the near term and even in the best of times, it helps to stay sharp in how you use your resources. In this issue Terry Ludlow, founder of Chipworks, looks at unconventional ways to make your IP do double duty. See if you are up to the heavy lifting in “When the Times Get Tough, The Tough Maximize IP Assets.” Next, for an extended brain workout, we begin a three part series by Sanjay Churiwala and Sapan Garg of Atrenta, and Chirag Gupta and Paresh Joshi of Texas Instruments. Be sure to make time for “Verification of Clock Domain Crossing in SoCs: Part One —Tools and Needs.” For a special RF exercise, there’s a new white paper featured on Chip Design, “The PSP Model in RF CMOS Design by Fujitsu Microelectronics America, Inc.” Then finish up with a quick, refreshing lap around the world of IP with our news briefs and other regular features.
"TLM-2.0 in Action" Tutorial Now Online
You are invited to a free video tutorial exploring the concepts and mechanics of the OSCI transaction-level modeling standard, TLM-2.0. Presented at the 2009 Design and Verification Conference, the tutorial's examples-based approach demonstrates how to get the most value out of using the standard.
When the Times Get Tough, The Tough Maximize IP Assets
By Terry Ludlow Chipworks' Founder and CEO, tludlow@chipworks.com
When times get tough, technology companies often look for unconventional ways to increase their revenues. Well run technology companies often have a wealth of intellectual property (IP) in the form of patents that constitutes a large portion of its corporate value; however, in all but a few companies this IP is underutilized as a means to support the business strategy. An effective patent strategy can contribute to the bottom line and increase market share for struggling companies.
In tough times it is common to scrutinize every budget and evaluate every asset. Individuals charged with managing a company’s patent program are often tasked to leverage patents more assertively and profitably or to consider selling them. Before acting, all IP professionals consider certain crucial points.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3302
Contemporary system on chip (SoC) designs invariably cover multiple application scenarios, and, in order to cover those scenarios, they have several clocks. Not just multiple clocks, but, some of these clocks are in different domains also; there is data-transfer across these multiple clock domains. While clock domain crossing (CDC) analysis at the block level by itself poses several challenges, doing a CDC analysis at the SoC level presents different kinds of challenges.
Hence, design teams have to look for certain additional characteristics in the tool. These requirements for additional characteristics arise, mostly due to specific peculiarities of the SoC.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=3303
Jul 26–Jul 31, 2009
San Francisco, California
Moscone Center
The world’s premier EDA and semiconductor design conference and exhibition. DAC features over 60 sessions on design methodologies and EDA tool developments, plus the NEW User Track presentations. The exhibition includes leading EDA, silicon and IP providers.
www.dac.comSynopsys, Inc. has acquired the Analog Business Group of MIPS Technologies, Inc. for $22 million in cash. The acquisition expands Synopsys' DesignWare intellectual property (IP) portfolio with a new family of analog IP such as Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs and Power Management. It will also add HDMI TX and RX protocols to Synopsys' existing interface IP solution. The acquisition gives access to a broad portfolio of high-quality interface and analog IP that supports the latest connectivity standards, process technologies and foundries—all from a single vendor. The company expects this acquisition will provide customers with a strong interface and analog IP portfolio that is silicon-proven, shipping in volume and unmatched in the industry.
Synopsys, Inc. >> www.synopsys.com/
SEMICON West is the must-attend event of the year! See the latest products and technologies for high-tech manufacturing. Meet the people moving electronics innovation. Explore developments in 3D IC design and TSV packaging. Discover opportunities in MEMS, flexible and printed electronics, solid state lighting, and nanoelectronics at the new Extreme Electronics. Find solutions to increase productivity, improve performance, and advance product development.Check out the Infinite Possibilities July 14-16, 2009, Moscone Center, San Francisco, CA.
www.semiconwest.orgCoWare, Inc. and Carbon Design Systems have formed a strategic partnership to deliver implementation-accurate models of ARM IP targeted for CoWare’s SystemC-based design solutions. The models and model kits will include implementation-accurate solutions for the ARM Cortex-A9 processor, AMBA3 Interconnect (PL301) matrix, and more. The Carbonized processor models for the environment will be integrated and delivered as Processor Support Packages (PSPs) to customers without the need to have access to ARM RTL code. Features include: Platform software analysis; Debugger synchronization for multi-core designs; Debug accesses from processor to memory; and Support for SystemC Modeling Library (SCML) properties.
Carbon Design Systems >> www.carbondesignsystems.com
CoWare >> www.coware.com
As the number of IP cores in embedded SoC designs grows, current bus structures become complex and time consuming to design. In addition, memory access problems can arise because there are now multiple processors competing for memory resources. Sonics, Inc. has announced its Network for AMBA Protocol or SNAP. The product is a turn-key solution designed to simplify the on-chip bus design for complex embedded SoCs by turning multilayer bus designs into an IP block. The easy-to-use development environment allows developers to capture their design with little or no training. It is particularly suited for embedded wireless, home networking and automotive applications. Examples include 3G/4G baseband and WiMax baseband products femtocells; gateway and wireless routers; and automotive control and telematics.
Sonics, Inc. >> www.sonicsinc.com
The SPIRIT Consortium has approved the standard SystemRDL™ 1.0, a language for the design and delivery of registers to be used in IP blocks within electronic designs, for public release. Its semantics support the entire life-cycle of registers from specification, model generation, and design verification to maintenance and documentation. Registers are not just limited to traditional configuration registers, but can also refer to register arrays and memories. Benefits include increased productivity, quality, and reuse of complex digital systems, and enabled sharing of IP within and between groups by specifying a single source for the register description. Download the SystemRDL V1.0 standard at www.spiritconsortium.org/tech/docs/. Example files including IP-XACT source and SystemRDL source for the same components are available.
The SPIRIT Consortium>> www.spiritconsortium.org/tech/community_support/
Semiconductor Manufacturing International Corporation (SMIC) announced a set of 65-nanometer low leakage process IPs, including the preliminary version release of six memory compliers. This portfolio, which contains a number of new, ready-to-use IPs, follows the 65nm standard cell libraries that were released earlier this year. The six memory compilers enable the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers include memories optimized for very high performance and also optimized for performance and area. They were developed internally with rigid design methodology. The 65nm IP portfolio can be used to design a wide range of consumer applications such as mobile phones, personal media players, GPS, DTV, set-top boxes, and mobile storage devices.
SMIC >> www.smics.com
Faraday Technology Corporation announced its commercial USB3.0 physical layer (PHY) at UMC 0.13um high-speed (HS) process. Based on the USB 3.0 version 1.0 specification, functionally and electrically, it has a maximum speed of 5.0Gbps. To achieve the specification with trade-off between power and die size, the company reports carrying out sophisticated improvement in this PHY architecture, including new compensation circuits in the equalizer of receiver to eliminate the channel loss caused by the cable and trace wire in the board. Some other new architectures also work for clock data recovery and transmitter to make the eye diagram meet the specification in all conditions.
Faraday Technology Corporation >> http://www.faraday-tech.com
46th DAC Announces Keynote Speakers and Special Monday Keynote Panel
DAC announced its keynote sessions. Fu-Chieh Hsu, Vice President, Design and Technology Platform of Taiwan Semiconductor Manufacturing Company (TSMC) will deliver the Tuesday Keynote, entitled “Overcoming the New Design Complexity Barrier: Alignment of Technology and Business Models” at 8:30 a.m. on July 28. Bill Dally, Chief Scientist, NVIDIA Corporation will deliver the Wednesday Keynote on “The End of Denial Architecture and the Rise of Throughput Computing” at 11:15 a.m. on July 29. In a special Monday Keynote Panel, “Futures for EDA: The CEO View,” Lip-Bu Tan of Cadence Design Systems, Inc., Walden C. Rhines of Mentor Graphics Corp. and Aart J. de Geus of Synopsys, Inc. will discuss industry futures with respect to markets, business and technology at 4:30 p.m. on July 27. DAC will take place July 26 – 31, 2009 at Moscone Center in San Francisco. More details are available at: www.dac.com.
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Design Automation Conference to Offer Engineering Scholarship Program
Applications for the annual “DAC Alumni Scholarship” program will be accepted through Friday, June 26. The Alumni Scholarship program is open to integrated circuit (IC) design and electronic design automation (EDA) engineers who are between jobs and without personal resources or corporate support for their DAC attendance. The program will enable up to 50 qualified engineers to attend this year’s DAC, which will be held July 26-31 at the Moscone Center in San Francisco. An additional 15 qualified engineers, currently ACM/SIGDA members, will be supported through a separate grant from ACM’s Special Interest Group on Design Automation. Additionally, exhibit passes will be awarded to all qualified applicants who do not receive a full scholarship. Applications must be submitted via an online confidential form found on the DAC website: www.dac.com.
Recipients of scholarships will be notified by July 9.
Analog design in silicon, though dwarfed by digital design efforts, is still very time consuming and requires a high level of design expertise. Meanwhile the need for well-designed analog circuitry is accelerating, driven by the explosion of wireless products and an increasing need for sensor interfaces in medical, automotive, industrial, consumer and other applications. John Wright makes a case for one solution in his “Analog Arrays Accelerate Analog Integration in ICs.”
Featured Story >> http://www.chipdesignmag.com/display.php?articleId=939
Analog, radio-frequency, and wireless design challenges have moved to the forefront of both chip and board-level design concerns. In this analysis our editor in chief, John Blyler, gives as example of one company’s approach to the chip and board-level issues facing analog-RF-wireless engineers. Time to tune in to “RF Board Designers Confront Many Challenges.”
Featured Story >> http://www.chipdesignmag.com/display.php?articleId=1127
SuperSpeed USB Developers Conference
Four Seasons at Chinzan-so in Tokyo, Japan
May 20-21, 2009
http://www.usb.org/developers/events/ssusb_devcon/
International Symposium on Circuits and Systems (ISCAS 2009)
Taipei International Convention Center, Taipei, Taiwan
May 24–27, 2009
http://www.iscas2009.org/
IMEC Technology Forum 2009 (ITF2009)
Crowne Plaza Hotel “Le Palace’, Brussels
June 2–4, 2009
http://www.itf2009.be/
Linley Tech Seminar: High-Speed Interconnects
DoubleTree Hotel, San Jose, CA
June 3, 2009
http://www.linleygroup.com/Seminars/hsi2009c.html
International Symposium on Rapid System Prototyping
Paris, France
June 23–26, 2009
http://www.rsp–workshop.org/
IEEE International Conference on Application–specific Systems, Architectures and Processors
Radisson Hotel Boston, Boston, MA
July 7–9, 2009
http://www.asap–conference.org/
SEMICON West 2009
Moscone Center, San Francisco, CA
July 14–16, 2009
http://www.semiconwest.org/
ASQED 2009 (Asia Symposium on Quality Electronic Design)
KL, Malaysia
July 15–16, 2009
http://www.isqed–asia.org/
SAMOS IX: International Symposium on Systems, Architectures, Modeling and Simulation
Samos, Greece
July 20–23, 2009
http://samos.et.tudelft.nl/samos_ix/
IWLS 2009 (International Workshop on Logic & Synthesis)
Cadence Research Laboratories,
Berkeley, California
July 24–26, 2009
(Co–located with DAC).
http://www.iwls.org/
System Level Interconnect Prediction 2009
Moscone Center, San Francisco, CA
July 26–27, 2009
(Co–located with DAC)
http://sliponline.org/
IEEE Symposium on Application Specific Processors, SASP 2009
San Francisco, California
July 27–28, 2009
(Co–located with DAC)
http://www.sasp–conference.org/
46th Design Automation Conference (DAC)
Moscone Center, San Francisco, CA
July 26–31, 2009
http://www.dac.com
IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2009)
Cancun, Mexico
August 2–5, 2009
http://www–elec.inaoep.mx/mwscas2009/
Signal and Image Processing (SIP 2009)
Honolulu, HI
August 17–19, 2009
http://www.iasted.org/conferences/home–654.html
Euromicro Conference on Digital System Design
Patras, Greece
August 27–29, 2009
http://www.iuma.ulpgc.es/dsd09/
International Workshop on Reconfigurable and Multicore Embedded Systems (WoRMES' 2009)
Vancouver, Canada
August 29 – 31, 2009,
http://embedded.cs.ccu.edu.tw/WoRMES2009/
(held conjunction with The IEEE/IFIP International Conference on Embedded and Ubiquitous Computing)
International Conference on Field Programmable Logic and Applications
Prague, Czech Republic
August 31 to September 2, 2009
http://fpl2009.org/index.php
SBCCI2009, Symposium on Integrated Circuits and Systems Design
Piramide Natal Resort and Convention, Natal, Brazil
August 31 to September 3, 2009
http://www.lasic.ufrn.br/chiponthedunes2009/sbcci/
Intel Developers Forum US, San Francisco
Moscone Center West, San Francisco, CA
September 22–24, 2009
http://www.intel.com/IDF/
ARM Developers’ Conference 2009
Santa Clara Convention Center, Santa Clara, CA
October 21-23, 2009
http://www.rtcgroup.com/arm/2008/
IP–Embedded Systems Conference 2009
Grenoble, France
December 1–3, 2009
http://www.design–reuse.com/ipesc09/
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
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