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Welcome to the September issue of the IP Designer & Integrator. Our role is to complement Chip Design magazine by providing semiconductor IP news, opinions, and articles. There are subscribe and unsubscribe options at the end of the page.
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Gervais Fong kicks off this issue with an explanation of how a good choice in PHY can ensure your project’s facility in handling the most successful connectivity standard in history. Why is it so successful? Consider Gervais' take in “How Advanced USB Standards Address Power, Area, and Performance.” Making sure the IP plays well with others, is part of David Schwan’s purpose in life. Let him explain “Why Is the GSA’s New AMS/RF Process Checklist Useful?” Then consider what Ed Sperling learned at a GSA panel just last week. When people talk, Ed listens, and then writes down the best thoughts. Ed ponders who’s to blame when IP doesn’t work and decides “Fixing Yield Problems Isn’t Always Intuitive.” Our only conclusion is our regular supply of news briefs and other features.
Today’s IP choices for the Universal Serial Bus (USB) cover many different types of interfaces for a wide variety of applicationsÑincluding portable consumer products. Power consumption and small form factors are key issues. SoC designers must also consider new requirements imposed by smaller technology nodes, especially for the USB PHY. As the most successful connectivity standard in history, USB has expanded from connecting PCs and PC peripherals to flash storage, digital imaging, audio and video, wireless, automotive, and now to tremendous growth in mobile phones. A force behind this growth are the ongoing enhancements to the USB standard, including the PictBridge specification that supports direct connections between printers and digital cameras and most recently, the High Speed Inter-Chip (HSIC) and Link Power Management (LPM) standards that lower power, area and enable chip-to-chip connectivity with USB. We will also begin to see the emergence of the USB 3.0 standard, which can deliver over 10 times the speed of today’s USB 2.0 connection.
Issues such as power consumption and small form factors in consumer products drive many of the key USB challenges for the design community today. The recent USB High Speed Inter-Chip (HSIC) standard makes it easier to interconnect other functionality that has been partitioned into multiple chips. USB HSIC offers an easy way to connect many different types of functions in a system. Since USB is already used extensively to connect products using the traditional USB cable, it is a good choice to move inside the system and act as a high speed chip to chip interface. For example, USB HSIC can be used to connect an embedded webcam, GPS, or Wifi chip to an applications processor within a smart phone or small form- factor embedded PC. Significant time and cost is saved because USB drivers and firmware that work with traditional USB 2.0 systems can be reused in USB HSIC applications.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=2649
eSilicon, a pioneering semiconductor Value Chain Producer (VCP), provides a comprehensive suite of custom chip design, productization and manufacturing services, enabling a flexible, low-cost, lower-risk path to volume chip production.
eSilicon >> http://www.esilicon.com/
Why is GSA's new Analog/Mixed-Signal/Radio Frequency (AMS/RF) Process Checklist of use to an Intellectual Property (IP) designer or IP integrator?
Scenario 1: You are a marketing manager at a small IP company, and you’ve been tasked with determining whether your IP block can be ported to process “X” and to another foundry at the request of one of your customers. You locate two stacks of foundry documents — one for the existing process in which the IP block is in, and another for the target process — and begin the tedious practice of looking for commonality between the two processes.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=2655
EVE is the leader in Hardware/Software Co-Verification. Nine of the top 10 semiconductor companies rely on ZeBu to verify their SOCs. With the best ROI on the market, ZeBu is also the choice of startups that need first-pass silicon success.
Eve >> EVE
Who’s to blame when IP doesn’t work?
That question is asked frequently at the most advanced process nodes. And the solution isn’t always as clear as it first appears.
Full Story >> http://www.chipdesignmag.com/display.php?articleId=2656
The National Science Foundation (NSF) and Semiconductor Research Corporation (SRC) announced a joint initiative for multi-core chip design and architecture. The three-year program will focus on several components of multi-core system architecture design. About $6 million in funding is available to U.S. universities, who have been invited to submit research proposals in key areas. These include Computer-Aided Design for multi-core systems, such as acceleration of design automation tools via multi-core platforms; interconnect, packaging and circuit techniques for multi-core; and low-power innovations. Dr. Sankar Basu, NSF program director, said that “CMOS scaling is increasingly limited by the realities imposed by physics, making architectural innovations critical to achieving increased computational performance. Multi-core-based systems promise computational performance enhancements and power reduction for both high- and low-end computing platforms.”
Semiconductor Research Corporation >> www.src.org
National Science Foundation >> www.nsf.gov
Intrinsity Inc. has signed an agreement with the System LSI division of Samsung Electronics Co., Ltd. to develop high performance, low power processors using the Intrinsity Fast14 technology. This approach combines 1-of-N Domino Logic (NDL), custom and semicustom static logic, high-speed memory technology, specialized low-power design techniques and a design automation platform. Fast14 technology includes a combination of process specific libraries, circuit technologies, specification languages and a set of tools that help automate the design flow. Since the technology integrates easily with conventional design styles, sophisticated SoCs can be rapidly built to serve a broad array of market needs at optimized performance/power operating points.
Intrinsity >> www.intrinsity.com
IPextreme Inc. is offering a new synthesizable IP core that implements the upcoming IEEE 1149.7 standard. This standard, which will be ratified in early 2009, will provide designers with powerful extensions to the current IEEE 1149.1 (JTAG) standard, uses fewer pins and maintains compatibility with IEEE 1149.1-based hardware and software. Features of the cJTAG Ð IEEE 1149.7 IP core include support for IEEE 1149.7 classes 0-5 (selected through hardware configuration parameter). It is partitioned along IEEE 1149.7-specified functional boundaries to extend processing unit (EPU) for class 0-3 operation and provides an advanced processing unit (APU) for class 4-5 operation. There is further parameterization within EPU and APU for class-specific and optional features and separate blocks for clock and reset signal conditioning.
IPextreme Inc. >> www.ip-extreme.com
CEVA, Inc. announced that Percello has licensed the CEVA-TeakLite-III DSP core for the development of advanced femtocell baseband chipsets. Femtocell access points are an emerging technology providing low-cost, fully integrated handset services for residential and small business environments. Percello's processor architecture leverages the fully programmable DSP core to deliver unprecedented levels of Femtocell performance and functionality. It provides an ideal feature set and power/performance balance for Femtocell requirements. The technology is expected to have a tremendous impact for the provision of wireless voice and data services in the next few years.
Percello >> www.percello.com
CEVA, Inc. >> www.ceva-dsp.com
Eureka Technology Inc. has released a DDR3 SDRAM controller core for ASIC/SoC applications. It includes fast page access, pipeline design and smart arbitration and supports both DDR2 and DDR3 SDRAMs to enable a smooth transition between the two technologies. The highly programmable IP core is licensed in Verilog or VHDL RTL code format. It is synthesizable to virtually any ASIC and FPGA technology and supports the standard DFI PHY interface for easy system integration. Optional features include different user interfaces such as AXI, AHB and generic user interface. The core is available as a single port SDRAM controller or a multi-port SDRAM controller with different bus interfaces at different bus clock speed sharing the same memory.
Eureka Technology >> www.eurekatech.com
LogicVision, Inc. has expanded its sales and customer service in Europe with the addition of Amblot SARL as an exclusive manufacturer's representative in southern Europe. The company provides complete silicon test IP and methodology that spans SoC design and manufacturing test based on proprietary BIST technologies for logic, memory and high-speed I/O. Its technologies enable SoC design teams to achieve single-digit DPM (defects-per-million) quality levels, accelerate time to working silicon--by reducing silicon bring-up times from months to days, lower test preparation costs, and reduce device test times, thus significantly improving product margins. Amblot, with its office located in Paris, France will be able to sell the company’s complete line of test solutions.
Amblot >> www.amblot.com
LogicVision >> www.logicvision.com
DDR3/DDR2 IP cores, as updated in our news brief, can “future-proof” SoC designs to keep up with changing standards. Jody Defazio covers the ins and outs of using them effectively in “Consumer Electronics are changing the face of DRAMs.”
Featured Story >> http://www.chipdesignmag.com/idesign/
The problem with using IP cores to ensure the future is that the added complexity can put your present at risk. In Clive (Max) Maxfield’s column, “Max’s Chips and Dips: Ignios and SystemWeaver,” he considers the complexity of SoCs with multiple uP cores, DSP cores, hardware acceleration engines, and a promising tool path.
Featured Story >> http://www.chipdesignmag.com/idesign/
SAME 2008 Forum
11th Edition Sophia Antipolis forum on MicroElectronics Conference Program
ESPACES ANTIPOLIS, Sophia Antipolis, France
October, 1 & 2, 2008
http://www.same-conference.org/
Suppliers Expo & Conference
Santa Clara Convention Center, Santa Clara, CA
October 2, 2008
http://www.gsaglobal.org/suppliers_expo/usa2008/
Semicon Europa2008
Stuttgart Trade Fair Centre, Stuttgart, Germany
October 7-9, 2008
http://www.semiconeuropa.org/
ARM DeveloperÕs Conference
Santa Clara Convention Center, Santa Clara, CA
October 7-9, 2008
http://www.rtcgroup.com/arm/2008/
18th Annual Research Business Forum (IMEC)
SAS Royal Hotel, Brussels, Belgium
October 15-17, 2008
http://www.arrm.be/home.aspx
Intel Developer Forum
Taipei, Taiwan
October 20-21, 2008
http://www.intel.com/idf/
Embedded Systems Conference Boston
October 27-30, 2008
Hynes Convention Center, Boston, MA
http://www.embedded.com/esc/boston/
International System-on-Chip Conference
Radisson Hotel, Newport Beach, CA
November 5-6, 2008
http://www.savantcompany.com/SoC6-Nov08/main.htm
IEEE Globecom 2008
Hilton Washington, Washington DC
November 30-December 4, 2008
http://www.ieee-globecom.org/2008/
IP08 IP Based Electronic System Conference & Exhibition
World Trade Center, Grenoble, France
December 3-4, 2008
http://www.design-reuse.com/ip08/
FPGA Summit
Wyndham San Jose Hotel, San Jose, CA
December 10-11, 2008
http://www.fpgasummit.com/
GSA Awards Dinner Celebration
Santa Clara Convention Center, Santa Clara, CA
December 11, 2008
http://www.gsaglobal.org/events/2008/1211/
IEEE Sensor Applications Symposium
17-19 February 2009
New Orleans, Louisiana, USA
http://www.sensorapps.org/
Editor: Jim Kobylecky, jkobylecky@extensionmedia.com
Editorial Director: John Blyler, jblyler@extensionmedia.com
Advertising/Sponsorship Opportunities: Karen Popp, kpopp@extensionmedia.com
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