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Welcome to the May of 2008. Our role is to complement Chip Design magazine by providing semiconductor IP news, opinions, and articles. There are subscribe and unsubscribe options at the end of the page.
True Circuits develops and markets a broad range of timing IP. TCI’s robust state-of-the-art circuits, methodical and proven design strategy, and close association with the world's leading fabs, IDMs, and design services companies allow it to quickly and reliably produce new and innovative PLLs and DLLs in a variety of advanced process technologies. Call (650) 949-3400 or visit the timing experts at http://www.truecircuits.com/cdIP1.
In this issue, Elie Massabki explains what we need to know about PCI Express standards. Carefully done, you can greatly expand the functionality of system without exceeding cost and complexity limits. Next Angela Sutton observes that the use of FPGAs for verifying or implementing complex SoCs requires an enlightened approach to IP within the design process. Then we follow with news abstracts from around the industry.
Ever considered PCI Express® (PCIe) connectivity for your next design and wondered whether it made sense for your application? Have you been discouraged by the multiple changes to the standard and continual increases in bandwidth that promise to add complexity and cost to your system? Or have you decided to migrate to PCIe, but can’t figure out how to implement your design?
Don’t worry; you’re not alone. Many designers are asking the same questions. The good news is that migrating to PCIe is less daunting than it initially appears. Here are a few answers to help get you started.
PCIe was created to supersede PCI and PCIX and to provide a high-speed and low pin-count interface to PC and server chipsets. Its developers envisioned a bus that would also be used inside communication systems, such as routers and switches, to replace proprietary backplane and chip-to-chip interfaces, as well as industrial systems ranging...
Full Story >> http://www.chipdesignmag.com/display.php?articleId=2205
A recent survey conducted anonymously by Synplicity to FPGA designers revealed wide scale use of system level components and Intellectual Property cores (IP). Over 30 percent of designs deployed complex IP including microprocessors.
FPGAs are appealing to ASIC designers. Some are for the first time choosing to implement the next generation of their product in an FPGA instead of an ASIC. Others are choosing to first verify their ASIC design by implementing the hardware for their system in an on-board FPGA. These designers require the very IP that they used or plan to use on their ASIC now be available for an FPGA.
The benefits of embedded IP in FPGAs are many: The ASIC designer can re-use their system software investment from the ASIC if they are now migrating to an FPGA. If new software development or hardware/software tuning is required for the next generation ASIC that you are designing, you can now get a head start on system...
Full Story >> http://www.chipdesignmag.com/display.php?articleId=2206
Virage Logic Corporation is adding Common Power Format (CPF) enabled 65-nm Standard Cell logic libraries to help customers manage low-power design projects in mobile consumer applications. CPF technology views identify specialized cells available in the library to enable advanced power saving capabilities. Included are always-on cells, isolation cells, level shifter cells, power switch cells and state retention cells to support a full range of advanced low-power techniques. CPF, a Silicon Integration Initiative (Si2)-standard power intent format, is used for specifying power-saving techniques early in the design process, thereby allowing sharing and reuse of low-power intelligence throughout the design process. CPF enables that data to be used consistently from RTL to GDSII.
Virage Logic >> www.viragelogic.com
Synplicity, Inc. introduced System Designer, its device-independent intellectual property (IP) configuration and system-level assembly environment that has been added to the company’s Synplify Pro and Synplify Premier FPGA design implementation tools. Users can select, configure and assemble internal and third-party IP delivered in the IP-XACT format, integrate that IP and then easily implement it into a variety of FPGA vendor devices, including those from Actel, Altera, Lattice Semiconductor and Xilinx. The environment is a key component of the company’s ReadyIP Initiative, which takes aim at simplifying the access, evaluation and use of IP for FPGA-based system designs. Users can evaluate and “try-before-they-buy” IP within their designs through these tools.
Synplicity >> www.synplicity.com.
TranSwitch Corporation announced what it states is the first HDMI 1.3 IP core operating at up to 10.5 Gbps (3.5Gbps per channel). It is available in 90 nm CMOS technology in two versions. The first meets all the current HD (High Definition) standards up to 2.25 Gbps. The second supports serial communications at a speed of up to 3.5 Gbps per channel for extended HD resolutions, with backward compatibility to the first version of 2.25 Gbps. The transmitter IP core and the DSP-based receiver IP core can run at aggregated speeds of up to 10.5 Gbps and support color depth of up to 16 bits, while providing exceptionally low power consumption and small die size.
TranSwitch >> www.transwitch.com
CEVA, Inc. announced its next generation DSP subsystem platforms for developers using the CEVA-X family of DSP cores. The platforms come in two versions, the CEVA XS-1100A optimized for wireless baseband applications, and the CEVA XS-1200A aimed at multimedia and other applications requiring high-performance signal processing. These configurable platforms use industry standard system buses, offering designers the ability to add their own hardware blocks or connect the DSP to other systems present on chip, making integrating the company’s cores straightforward and efficient. Both platforms support critical low power design requirements through smart Power Management Unit (PMU) technology, which includes automatic sleep/wake of each resource and matrix separately according to transaction type, source, destination, initiator and duration.
CEVA >> www.ceva-dsp.com
Synopsys, Inc. is offering DesignWare PHY IP for PCI Express 2.0 (Gen II), based on the PCI Express 2.0 base specification. PCI Express 2.0 doubles the 1.1 specification transfer speed from 2.5 Gbps to 5.0 Gbps per lane, meeting the demand for both increased bandwidth and narrower interconnect links in data center, storage, high-end graphics and networking infrastructure applications. The offering substantially exceeds the PCI Express 2.0 electrical specification in areas such as jitter, margin and receive sensitivity. It includes advanced built-in diagnostic capabilities and ATE test vectors enabling at-speed production testing of the PHY. It is implemented in standard CMOS digital technologies and does not require special process options.
Synopsys >> www.synopsys.com
MIPS Technologies, Inc. is teaming with the Faculdade de Engenharia da Universidade do Porto (FEUP), a leading school of engineering in Portugal, to further innovation and technical advancement in microelectronics. The multi-year agreement provides a foundation for enhanced educational research by the masters and doctoral programs of the school's Electrical and Computer Engineering Department. Through the program, a distinct group of graduate students will have access to MIPS Technologies' IP to conduct research in the areas of architectural design implementation, back-end synthesis and flows, peripheral interfaces, pipelines, co-processor development, user-defined instruction blocks, and other key areas that impact performance, power dissipation, cost, and critical time-to-market efficiencies in today's semiconductor devices.
FEUP >> www.fe.up.pt
MIPS Technologies >> www.mips.com
Kilopass Technology has signed an agreement with Dongbu HiTek to develop the company’s Extra Permanent Memory, or XPM, NVM one-time programmable IP for Dongbu's 0.18um and 0.13um CMOS process nodes. The agreement offers customers more advanced system architecture options. XPM technology uses proprietary standard logic CMOS process, requires no changes, and makes it easy for customers to implement secure key storage for applications like HDCP, calibration, and firmware storage across a broad range of application requirements. More customers are demanding higher security and post-production system configuration features, and these products provide the solution.
Kilopass >> www.kilopass.com
Dongbu HiTek >> www.dongbuhitek.com
In-silicon system instrumentation can include an IP-subsystem dedicated to control, trace and debug of embedded signals to give the user visibility and controllability of system interfaces and operations. Find out how in “OCP System In Silicon Instrumentation Solutions -- More Than Just Trace” by Dr. Neal Stollon.
Featured Story >> http://www.chipdesignmag.com/idesign/
Bob Tait maintains that the future looks bright for any company with a professional approach to the analog IP industry, especially for the few that have built strong portfolios of multi-generational products targeting applications requiring deep levels of integration at the leading edge technology nodes. See if he’s talking about your future in “The Analog IP Industry Comes of Age.”
Featured Story >> http://www.chipdesignmag.com/idesign/
Great Lakes Symposium on VLSI (GLVLSI 2008)
May 4-6, 2008
Radisson Resort Orlando-Celebration Hotel, Orlando, FL
http://www.glsvlsi.org/
IEEE International Symposium on Circuits and Systems
May 18-21, 2008
Sheraton Seattle Hotel, Seattle, Washington, USA
http://www.iscas2008.org/
2008 IEEE International Interconnect Technology Conference
June 1-4, 2008
San Francisco Airport Hyatt Regency Hotel, Burlingame, CA.
(preceded by a Short Course on advanced interconnect technology, June 1)
http://www.his.com/~iitc/
SEMICON Russia 2008
June 2-4, 2008
World Trade Center, Moscow, Russia
http://wps2a.semi.org/wps/portal/_pagr/126/_pa.126/399
45th Design Automation Conference (DAC)
June 8-13, 2008
Anaheim Convention Center, Anaheim, CA
http://www.dac.com/
IEEE International Conference Application-specific Systems, Architectures, and Processors (ASAP 2008)
July 2-4, 2008
Leuven, Belgium
http://asap-conference.org/
Semicon West
Moscone Center, San Francisco, CA
July 15-17, 2008
http://www.semiconwest.semi.org/
IEEE International MWSCAS 2008
August 10-13, 2008
Knoxville Convention Center, Knoxville, TN
http://www.eecs.utk.edu/mwscas/
IASTED International Conferences on Circuits and Systems (CS 2008)
August 18-20, 2008
Kailua-Kona, HI
http://www.iasted.org/conferences/home-625.html
Intel Developer Forum
Moscone Center West, San Francisco, CA
August 19-20, 2008
http://www.intel.com/idf/
Hot Chips
Memorial Auditorium, Stanford University
August 24-26, 2008
http://www.hotchips.org/hc20/
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