MAY 2008 |
[Max's Chips & Dips] Silicon Canvas Blows My Socks Off (iDesign Subscribers  ) Recently, I was chatting to the folks at Silicon Canvas, and I'm still trying to wrap my brain around all of the incredible things they've been working on in the field of automating analog layout. |
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 | Getting Practical about Semiconductor IP Reuse (iDesign Subscribers ) NXP’s CoReUse standard is an example of one company’s innovative approach to solving a very real and practical problem in the field of semiconductor design. |
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 | Max's Chips and Dips: Apache's New Chip-Package Solution (iDesign Subscribers ) Apache Announces Sentinel-PI, A Global Chip-Package-System Co-Design and Co-Analysis Solution for Power Integrity. |
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 | Design Data Management Improves Productivity - Even for Small Design Teams (iDesign Subscribers ) As demonstrated by the design of a very small, high-frequency analog component, even small teams working on small designs can realize significant productivity benefits by using Design Data Management (DDM). |
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 | Max's Chips and Dips: Automated, Full-Chip Mixed-Signal Design Solution (iDesign Subscribers ) Those clever little rascals at Magma never fail to have something interesting up their sleeves. |
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APRIL 2008 |
 | Max’s Chips and Dips: Silicon Canvas Thrills (iDesign Subscribers ) Recently, I was chatting to the folks at Silicon Canvas, and I'm still trying to wrap my brain around all of the incredible things they've been working on in the field of automating analog layout. |
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 | Max’s Chips and Dips: RFID from Medical Supplies to Bananas (iDesign Subscribers ) Universal, affordable, smart label RFID chip from IDS Microchip opens multiple new markets for automatic data-logging/tracking systems. |
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 | Max’s Chips and Dips: Chip-Package-Board Co-Design ... It’s a Brave New World (iDesign Subscribers ) In the case of today’s bleeding-edge SoC, Sip, PiP, and PoP components, it is no longer possible for the chip, package, and board design teams to work in isolation. |
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MARCH 2008 |
 | Methodology and Flow Challenges in System-level Co-design of Multi-die Packaged Systems (iDesign Subscribers ) Today’s designs require new robust design flows with concurrent capabilities that bridge the communication gap between the IC, Package, and PCB environments. |
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 | Coordinating from Silicon to Package (iDesign Subscribers ) A new IC/Package/Board co-design and co-verification methodology needs to be implemented to enable challenging System-in-Package (SiP) design techniques. |
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 | If you can’t measure progress against your plan, you have no plan! (iDesign Subscribers ) There are verification technologies available today that use markup languages to capture functional verification plans, enabling measurement of completion throughout a project. |
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FEBRUARY 2008 |
Max's Chips and Dips: Cool News from Agilent EEsof (iDesign Subscribers ) The 2008 release of Agilent EEsof''s Advanced Design System (ADS) software will make even grizzled engineers squeal like schoolgirls! |
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GHz Multi-technology Design: Buzzword or Game-Changer? (iDesign Subscribers ) In order to design out the issues associated with multi-technology design, design flows comprising people, process, EDA, and CAD tools must be implemented. |
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JANUARY 2008 |
 | Verification – the Next Step for ESL (iDesign Subscribers ) What if we write a high level collection of models and – when the collection "works" in its native software environment – compile it with some whiz-trick-tool that produces stellar RTL that is guaranteed to work whether simulated or not? |
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Bucking the Trend – Outsourcing to Canada, Eh (iDesign Subscribers ) Mixed-signal ASICs are in high demand these days. Finding a way to create such devices quickly, at lower cost and with reduced risk, is a never-ending search for many designers and their managers. |
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 | Max's Chips and Dips: Cool News from Agilent EEsof (iDesign Subscribers ) The 2008 release of Agilent EEsof''s Advanced Design System (ADS) software will make even grizzled engineers squeal like schoolgirls! |
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DECEMBER 2007 |
 | Generating C-code from MATLAB Functions (iDesign Subscribers ) Using the Catalytic Function Library and MCS, developers can automatically generate redistributable C code that is functionally equivalent to an original MATLAB algorithm. |
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 | Accelerating Simulation While Preserving a Familiar Verification Environment (iDesign Subscribers ) Deploying hardware acceleration has been enormously beneficial to the ASIC design group at Anchor Bay Technologies. The team can create and modify architectures much earlier in the design flow, and they now have the ability to do mixed-HDL logic simulation, simulation acceleration, and in-circuit emulation. |
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NOVEMBER 2007 |
| Max's Chips and Dips: "It's the Best Christmas Present Ever," said Max excitedly. (iDesign Subscribers ) Sand is pouring through the hourglass and time is racing by when it comes to buying Christmas presents, but don't despair, because I know just the thing... |
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 | Bringing non-volatile memory blocks to SoCs using the SONOS process (iDesign Subscribers ) Adding one particular type of memory technology to a CMOS IC – the non-volatile memory block – has historically been problematic for wafer fabs and IC designers, alike. |
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OCTOBER 2007 |
 | Layout Optimization for Yield -- A Case Study (iDesign Subscribers ) At sub-wavelength geometries, many yield-loss mechanisms manifest themselves as layout issues. If these hot spots are not addressed as early as possible in the flow, they impact both time-to-market and revenue. |
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 | A Truly Open Verification Methodology (iDesign Subscribers ) An open verification methodology supports multiple tools from multiple vendors and is freely available to any interested vendors, users, or standardization organizations. |
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 | Moving to Advanced Design Abstraction (iDesign Subscribers ) Today's changing design landscape is challenging existing design methodologies that have their roots in a traditional board-centric approach, where separate tools create the hardware and software elements from a 'circuitry-up' perspective. |
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SEPTEMBER 2007 |
 | Putting Together Win-Win-Win Migration Programs Makes Good Business Sense (iDesign Subscribers ) While an acquisition is a major win for two vendor suppliers, the needs of a customer or project team is often overlooked, leaving them without the support and service. The solution is ... |
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 | The Analog IP Industry Comes of Age (iDesign Subscribers ) The future looks bright for any company with a professional approach to the analog IP industry, especially for the few that have built strong portfolios of multi-generational products targeting applications requiring deep levels of integration at the leading edge technology nodes. |
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| Max's Chips and Dips - MATLAB-to-C Flow Supports State-of-the-Art EDA Tool Development (iDesign Subscribers ) Catalytic's MATLAB-to-C Synthesis Dramatically Increases Productivity, Quality, and Focus for the Manufacturing Modeling Group at Cadence |
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 | Building a Transaction-Based Acceleration Regression Environment (iDesign Subscribers ) Using a common verification environment for both software simulation and hardware acceleration, it is possible to achieve significant performance improvement, particularly for system-level verification when employing a solid testbench architecture and a well defined regression methodology. |
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AUGUST 2007 |
 | Creating an ESL Flow (iDesign Subscribers ) Adopting ESL methodologies has the potential for delivering a 10X return over 3-5 years as these processes mature. Improvements of that order in semiconductor design are necessary to reduce the cost of design to a more reasonable budget that can deliver business returns. |
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 | Case Study: Carbon Design Systems and iVivity (iDesign Subscribers ) "Carbon allows us to rapidly identify, fix and verify fixes in our software and makes me confident that we'll have software up and running the first day we get our chips back from fab." -- Jim O'Connor, Senior Vice President of Engineering, iVivity. |
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 | Chip Designers Must Think Like an Architect for Chip-Package Co-Design (iDesign Subscribers ) Chip designers need to incorporate package-aware optimization and tradeoff software into their design plan to test how a signal propagates through the die, the package substrate and the PCB. |
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JULY 2007 |
| Max's Chips and Dips: Seeing Black-and-White Schematics in Color (iDesign Subscribers ) Not-so-long-ago, I heard from an electrical engineer who says that he does indeed perceive AND, OR, NAND, NOR etc. logic gates in different colors when looking at black-and-white gate-level schematic diagrams. |
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 | OCP System In Silicon Instrumentation Solutions -- More Than Just Trace (iDesign Subscribers ) In-silicon system instrumentation can include an IP-subsystem dedicated to control, trace and debug of embedded signals to give the user visibility and controllability of system interfaces and operations. |
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 | Software-Powered Coherent Design (iDesign Subscribers ) With software escalation dictating a concurrent design flow, new requirements are imposed on the design team and the tools that compose the software powered design flow. |
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| Max's Chips and Dips: New Catalytic RMS-Based Flow Is An Unqualified Success (iDesign Subscribers ) Harris analysis group's use of Catalytic RMS enabled an early customer demonstration! It allowed them to dramatically accelerate their existing MATLAB models while still allowing them to use MATLAB's powerful visualization and analysis facilities. |
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 | Size Matters! (iDesign Subscribers ) EDA applications are inherently unable to handle the largest, most complex designs that users throw at them -- and for a very good reason... |
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| Max's Chips and Dips: Building a PCell-based Standard Cell Library (iDesign Subscribers ) The engineering team at CMC Technologies chose PyCell Studio when architecting their new technology, and found that it delivered a number of unanticipated productivity benefits in addition to exceeding their technical requirements. |
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JUNE 2007 |
 | Consumer Electronics are changing the face of DRAMs (iDesign Subscribers ) In order to "future-proof" current SoC designs in 2007, DDR3/DDR2 IP cores started to roll out in early 2007. These cores will allow SoCs to interface to either DDR3 or DDR2 SDRAMs, providing key flexibility to the end SoC and its customers. |
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 | The Evolution of Structured ASIC (iDesign Subscribers ) The pain that structured ASIC's were meant to alleviate has not gone away, but has gotten much worse. Yet most of the companies that introduced structured ASIC product lines have abandoned them. Why this paradox? |
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 | Meeting Aggressive Project Schedules with Fixed Design and Verification Resources (iDesign Subscribers ) Given that the methodology, tools, and expertise are available, an optimized scalable coverage-driven verification (SCDV) solution can be deployed and implemented today. Help yourself now with a higher leverage approach so that the smaller, but currently painful, problems no longer occur. |
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 | The Changing Nature of IP in the Electronics Industry (iDesign Subscribers ) Ten years ago, it wasn't clear whether advances in EDA or adoption of IP reuse would be the solution for what was called the "productivity gap". Now the market has voted and the answer is... |
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Soft IP Actually Does Exist for the Analog ASIC (iDesign Subscribers ) Via-configurable-array technology enables the rapid development and low-cost design of feature-rich, mixed-signal ASICs that integrate sophisticated analog IP blocks. |
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MAY 2007 |
| Max's Chips and Dips: IC Manage to the Rescue! (iDesign Subscribers ) Project management is said to account for 20 to 25 percent of design costs at the 65-nm process node, which is almost double the costs we saw at 90 nm; the solution is the GDP (Global Design Platform) from IC Manage. |
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 | Today's SoC Designs Demand a Customizable, Standalone Transistor-level Design Checker (iDesign Subscribers ) What is required is a common design checker that accepts the netlist file formats associated with all of the industry-standard A/MS simulators is fully customizable to allow users to add their own proprietary tests. |
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 | Divide and Conquer to Overcome Design Complexity in Consumer Applications (iDesign Subscribers ) Changing the way companies approach complex applications is becoming imperative to survive in the highly competitive consumer SoC world. Nothing less that a major shift in problem-solving techniques is needed to arrive at affordable and efficient SoCs to drive the products that continue to amaze us. |
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| Max's Chips and Dips: A Fabulous Flurry of Activity (iDesign Subscribers ) There has recently been a fabulous flurry of activity in the chip design community, such as the red-hot announcements from Clairvoyante, Novelics, Optimal, Tensilica, and Certess. |
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 | Towards Scalable Design Tools (iDesign Subscribers ) What we need are truly scalable design tools. In essence, this means that by simply increasing the number of CPUs used by a tool ("throwing more hardware at a problem") you can run larger designs in less time. |
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 | Coverage-Driven Methodology for SoC Development Critical for Success (iDesign Subscribers ) Dr. Andreas Dieckmann of Siemens AG presents a case study on adopting Specman "e", formal property and equivalence checking, emulation and prototyping, and the coverage driven methodology developed by his team for the verification of SoC projects. |
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 | A Platform Approach to Handle 90/65nm Technology Migration Challenges (iDesign Subscribers ) Disjoint analysis and verification steps will not serve the needs of designs created in the 90/65nm technology nodes; engineers desperately need an integrated analysis and verification platform. |
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 | Optimizing Chip Debug through Transaction Extraction with SystemVerilog Assertions (iDesign Subscribers ) Transaction-level debug provides the bridge between different abstraction layers and enables advanced bus analysis and early architecture exploration by representing complex signal behavior in a way that can be easily comprehended. |
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APRIL 2007 |
 | Unified Verification of SoC Hardware and Embedded Software (iDesign Subscribers ) To close the gaps in the verification process, it is necessary to treat embedded software more like the hardware; every corner case is important and every problem that can be found early leads to a savings later. |
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 | Achieving Success in an Increasingly Complex Design Environment (iDesign Subscribers ) The Value Chain Producer can play an increasingly important role in addressing the challenge of IP integration in today's chip designs. |
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 | Hardware-Assisted Verification: At What Cost? (iDesign Subscribers ) New verification solution is relevant and important for mainstream electronics designers; the investment in this solution is minimal compared to the high stakes and risk in delivering products that have not been completely verified. |
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 | Third-Party IP - Curse or Blessing to SoC Development? (iDesign Subscribers ) For successful SoC development, it is imperative that we begin to think of third-party IP in a new light. Not only must we redefine "quality" IP, but we must also open our thinking to the development and adoption of a fully integrated IP sub-system. |
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 | IP is an Industry (iDesign Subscribers ) The debate regarding the inclusion of semiconductor IP sales into the EDA industry numbers is continuing in the media. MOSAID is and always has been an IP company, and we say: "No - IP is not EDA." Here's why. |
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| Max's Chips and Dips: Elliptic Curve Cryptography (iDesign Subscribers ) Until recently, the most widely supported public key encryption scheme was RSA, but now there's a new kid on the block -- Elliptic Curve Cryptography (ECC) -- which is set to become the leading next-generation public key cryptosystem. |
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MARCH 2007 |
 | Multiple XDSL Flavors Challenge Chipmakers (iDesign Subscribers ) The rapid advancements in DSL technology over the past decade provide a major challenge to chip makers. In particular, the order of magnitude increase in data transmission rates provided by VDSL2 create substantial design challenges. |
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 | Who Is Verifying the Verifier? (iDesign Subscribers ) Functional verification can be thought of as an instrument used to measure the quality of the design. As with any measurement, it is standard practice to "calibrate" the instrument. But if we only calibrate the stimuli and not the response, doesn't this mean the verification environment is not calibrated? |
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FEBRUARY 2007 |
 | Customizable Synthesis Engine for Programmable Platforms (iDesign Subscribers ) A synthesis engine with customizable technology mapper and optimization engine can provide significantly higher QoR for the users of these platforms as compared to standard off-the-shelf synthesis tools. |
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| Max's Chips and Dips: I Can See Clearly Now (with Clear Shape) (iDesign Subscribers ) InShape generates real-world contours and uses them to identify potential catastrophic failures; OutPerform takes the real-world contours generated by InShape and uses them to identify potential parametric failures. This stuff is very, very clever! |
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 | Inherent Benefits of a Delta-Sigma Fractional-N PLL in Power-Conscious SoC Designs (iDesign Subscribers ) This paper compares and contrasts two types of PLLs, highlighting the benefits designers can exploit by using fractional PLLs in place of traditional integer solutions for system clocks. |
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 | Beyond Monte Carlo Analysis for Analog/Mixed-Signal, Custom Digital, and Memory Designs (iDesign Subscribers ) We must begin to move beyond the basic Monte Carlo analysis techniques to a more comprehensive and beneficial transistor-level statistical design and verification framework. |
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 | Is Your System-Level Project Benefiting from Collaboration or headed to Chaos? (iDesign Subscribers ) Without system-level planning and a holistic approach, you could be headed for project cancellation or a recall. |
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JANUARY 2007 |
 | Metric-driven Methodology Speeds the Verification of a Complex Network Processor (iDesign Subscribers ) How a small hardware verification team experienced an interesting example of how introducing new verification methodologies into a real world design environment can improve overall productivity and process management. |
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 | The Importance of Design Analysis in FPGA Synthesis (iDesign Subscribers ) Design analysis capability now is its own category in user surveys, ranking as high in importance as obtaining Fmax and good circuit area results out of synthesis -- an area where third-party synthesis tools can do a better job than synthesis tools from FPGA vendors. |
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 | Interoperable PCell Libraries Or Bust! (iDesign Subscribers ) The first company to deliver an Interoperable PCell Library (IPL) with advanced passives and support for multiple EDA vendor tools will have a distinct advantage when competing for the next generation of chips aimed at consumer electronics. So, who will be the first to offer this IPL? |
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 | The Power of RTL Clock-gating (iDesign Subscribers ) Sequential Equivalence Checking can verify clock-gating, giving designers the confidence to make aggressive power optimizations late in the design process. The result is a lower power, higher quality design. |
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 | Dummy Fill Needs to Wise Up (iDesign Subscribers ) A purpose-built tool for fill synthesis can allow designers to achieve an optimal fill solution, simultaneously meeting the needs of manufacturability while maintaining device performance. |
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 | Focusing on Primary ESL Design Solutions (iDesign Subscribers ) Early ESL design tools often failed to deliver on their promises, but designers and EDA vendors have carried on, and the electronics industry now has a stable of quality ESL tools to help conquer the design complexity issue. |
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DECEMBER 2006 |
| Max's Chips and Dips - Embedded Developers Should Be Ahead of the Curve . . . Not Behind It! (iDesign Subscribers ) It's time for embedded hardware and firmware/code developers to be dragged kicking and screaming into the 21st Century! |
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| Can ESL Synthesis Make High-Level Modeling Relevant? (iDesign Subscribers ) Ideally, a model should serve a dual purpose; it should be used to provide decision support for architectural choices, and later it should become the foundation of a virtual platform for some level of software development and testing. |
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 | Transaction-Level Modeling Gains Further Momentum (iDesign Subscribers ) TLM is one of the catalysts driving the acceleration of electronic system level (ESL) design methodology, as designers are using TL models for system modeling, verification, and most recently system and hardware design and implementation. |
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 | Embedded Systems Development: We Must Support Standards and Deliver Open Development Environments (iDesign Subscribers ) Companies delivering embedded system design tools must invest in the development of solutions that address both design and supply chain challenges – when customers win, we win! |
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NOVEMBER 2006 |
| Max's Chips and Dips: Escape from Analog Alcatraz (iDesign Subscribers ) Although incredible useful, analog PCells have (until now) effectively been "restrained behind bars." Enter those little scamps at Ciranova, who have just unlocked the door and thrown away the key! |
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 | The Man With The Twisted IP [TWIS] (iDesign Subscribers ) Sherlock Holmes pointed the way. We realized we needed data about that IP, and lots of it. It quickly became apparent that all information required to make rational design decisions didn't exist in one place or one format... |
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OCTOBER 2006 |
| Max's Chips and Dips: Prisoner PCell Block A (iDesign Subscribers ) My *lack* of knowledge with regard to the analog domain is encyclopedic, so I was enthralled to be regaled with a tale so terrible as to make even the strongest amongst us quiver at the knees. |
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 | Transaction-Level Modeling is Critical for an Effective Functional Verification Methodology (iDesign Subscribers ) Complexity drives greater degrees of abstraction, driving the shift in focus from the register transfer level to the transaction level. Consequently, the most successful advanced verification methodology will be one which is based upon transaction-level modeling (TLM). |
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 | Emulation Gets the Nod vs. FPGA Prototyping (iDesign Subscribers ) System-level verification solutions require power of emulation to address the opposing forces of increasing complexity and shrinking design schedules |
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SEPTEMBER 2006 |
 | Be Early with Power (iDesign Subscribers ) Traditionally, costs associated with packaging and cooling have been the key drivers for pulling power within an acceptable range. However, several other considerations are driving the need for low power devices today. |
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| Max's Chips and Dips: S3 is the one for me! (iDesign Subscribers ) Silicon chips designed by S3 are to be found in 35% of the world's cell phones, which is not a shabby achievement whichever way you look at things! |
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 | What's Your Verification Game "Plan"? (iDesign Subscribers ) Imagine knowing what impact adding or removing features will have on your milestones. Imagine finishing your design on time with less stress. Well, it's time to quit imagining and give this new planning methodology a try on your next project! |
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 | EDA Vendors: "Service your Customers" (iDesign Subscribers ) Pre-developing and licensing key re-usable EDA modules provides a new way to think about solutions that move away from a common off-the-shelf product model to a more customer-centric customized tool development model. |
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AUGUST 2006 |
 | Inexpensive Protection of Digital Content (iDesign Subscribers ) Picking the right non-volatile memory to implement digital content protection could mean the difference between a successful, profitable product and one that languishes on store shelves. |
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 | Case Study: SwitchCore's deployment of Simics from Virtutech (iDesign Subscribers ) Companies that choose to subscribe to a concurrent development methodology will find themselves reaping the benefits of a virtualized development approach: shorter development schedules, lower project costs, reduced risk and higher product quality. |
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| Max's Chips and Dips: Embedding Security in your Designs (iDesign Subscribers ) Certicom have come up with a rather cunning way to protect your chip designs throughout the manufacturing process, thereby potentially saying you millions of dollars! |
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| The ROI of DFM? (iDesign Subscribers ) With all of the challenges that are facing designers of sub-100nm chips today, why is there so much skepticism about the value of DFM products? |
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| Max's Chips and Dips: Cool "Stuff" from Kilopass and Cadence (iDesign Subscribers ) I'm always happy when I'm learning something new, so I'm currently bouncing off the walls with excitement because there's so much cool "stuff" happening at the moment! |
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 | Class D Amplifiers Empower Mobile Multimedia (iDesign Subscribers ) In order to meet growing consumer demands for flexible audio features and hi-fi sound from mobile terminals, designers of handset audio chips are optimising the class D amplifier to meet the special noise and power management demands of mobile application |
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JULY 2006 |
 | The AVAD Search for Perfection in Analog and Mixed-signal Design (iDesign Subscribers ) What analog / mixed-signal designers need is a suite of tools that work with all industry-standard simulators, simulation file formats, and simulation environments to provide complete analysis, verification and debugging (AVAD). |
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 | Leakage Power and Variability Reduction in a Mobile Baseband Processor (iDesign Subscribers ) An engineering team at Qualcomm describe how they used the Blaze MO optimization software from Blaze DFM to significantly reduce leakage power and improve parametric yield. |
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| It's time to abstract higher-levels of performance from your verification process (iDesign Subscribers ) In this article, Ran Avinun of Cadence Design Systems provides an overview of the advantages of using Transaction-based System Verification (TBSV). |
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| Max's Chips and Dips: Magma's Automated Chip Creation now Package-Aware (iDesign Subscribers ) It doesn't take a genius to realize that combining an automated chip creation environment like Talus with a tool like RioMagic that works on the chip and the package designs concurrently has to be a jolly good idea. |
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JUNE 2006 |
 | Concurrent Layout and Package Design for Deep Sub-micron ICs (iDesign Subscribers ) Rio Design Automation has developed a product, RioMagic, to enable the layout of the die within the context of the external environment, specifically the package substrate and the PC Board connections. |
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| The Looming Gap between Design Debugging and Results Analysis (iDesign Subscribers ) With existing tools for analog and mixed-mode chips, a gap is beginning to loom between design debugging and results analysis; bundled solutions with "good enough" waveform analysis are not going to bridge this gap efficiently. |
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| Max's Chips and Dips: Wow! There's so much going on! (iDesign Subscribers ) There's so much going on at the moment that I can barely keep track of things, with mega-cool announcements from companies like Lynguent, Mentor, Solido, and Synplicity. |
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 | Cisco Evaluation of InCyte as a Standard Chip Estimation Methodology (iDesign Subscribers ) Estimation results from InCyte for two ASIC designs are compared with the results from actual silicon and with an existing estimation methodology. |
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| Electrical DFM -- Focusing on What Matters to Chip Designers (iDesign Subscribers ) Do chip designers really care about design for manufacturability (DFM) and yield? Dave Reed of Blaze DFM thinks that if they don't, they need to! |
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| Max's Chips and Dips: Mentor Launch Catapult BL and SL (iDesign Subscribers ) Ever since I first ran into it, I've had a lot of respect for the Catapult tool(s) from Mentor. Originally known as Catapult C, this little scamp has recently been super-charged and re-presented as two products: Catapult BL and Catapult SL. |
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MAY 2006 |
 | Advances in IC Optimization Accelerate Path to Design Closure (iDesign Subscribers ) Intelligent optimization algorithms, embedded analysis and extraction, and distributed multi-processing are required to provide the accuracy and extreme speeds required to address nanometer-scale chip complexity. |
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 | RTL++ and The Return of the Tall Thin Designer (iDesign Subscribers ) A new and broader definition of register-transfer level (RTL) design is emerging that puts new demands on logic designers and creates new opportunities for designers to add value and distinguish themselves. |
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| Inclusive Design and Verification Methodologies will Drive Next Generation SoCs (iDesign Subscribers ) It will take metrics, management, and an overall process that is language inclusive, not exclusive, to drive the successful delivery of our next generation system-level designs. |
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| Max's Chips and Dips: A New DFM Company Blazes Into View (iDesign Subscribers ) A recently announced company, Blaze DFM, intends to set the EDA industry on fire with a new design for manufacturing concept called "Electrical DFM". |
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| The Changing Face Of Re-Usable IP (iDesign Subscribers ) If complexity and gate count are approximately correlated, then IP is becoming about 5 times more complex every 3 years. |
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 | For Better Designs, Add SPICE to Taste (iDesign Subscribers ) A new and innovative approach to high-integrity post-layout verification is critically needed, in order to correctly consider the complex and dynamic circuit interactions caused by tight coupling. |
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| Max's Chips and Dips: Xilinx Unveils new Virtex-5 FPGA Architecture (iDesign Subscribers ) Xilinx has just announced the fifth generation of its Virtex FPGAs, and these new Virtex-5 devices are simply incredible. |
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| Max's Chips and Dips: Books on the EDA Universe (iDesign Subscribers ) Two meaty new books on EDA for design, verification, test, and physical implementation are targeted towards engineers in the trenches working on state-of-the-art silicon chips. |
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| ESL Lives Up to Its Early Promise in Embedded Systems Design (iDesign Subscribers ) There is a new frontier for ESL design: complex embedded systems demand new design methodologies and tools that satisfy the needs of hardware and software design. |
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Design-Centric Process Characterization (iDesign Subscribers ) A design-centric process characterization methodology provides a platform for designers and manufacturers to collaborate towards ramping yields. |
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APRIL 2006 |
 | The Effects of the iPOD on IC Design (iDesign Subscribers ) Instead of selling one cell-phone to someone for three years, now there is a chance to sell them three cell-phones in one year. |
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| Max's Chips and Dips: The Computing Universe (iDesign Subscribers ) There are fundamentally three different ways of performing computations, from a great big hairy single-core processor to a great big "pile of gates", with a plethora of esoteric architectures in-between. |
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 | A new route to improving time-to-yield (iDesign Subscribers ) Improving yield is key to the profitability of high volume memory chip design, but there is a better way to enhance time-to-yield than just throwing design for manufacturing tools at the problem. |
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 | The Death of the Structured ASIC (iDesign Subscribers ) My list of the worst semiconductor products would include the Structured ASIC, a device that is not fictitious and is not a joke, but deserves to be one. |
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 | The Emergence of EDA Component Software (iDesign Subscribers ) With help from an EDA component software vendor, an entrepreneur with a keen sense of timing and a good idea can now focus attention on the challenge at hand. |
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 | A comparison of Network on-Chip and Busses (iDesign Subscribers ) With increasing SoC complexity and performance, the NoC is clearly the best IP block integration solution for high-end SoC designs today and into the foreseeable future. |
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| Max's Chips and Dips: Stratosphere Solutions and Zenasis Technologies (iDesign Subscribers ) Zenasis have cool tools for wringing the last drop of performance out of a design, while Stratosphere provide the tools to make sure the ensuing chips actually work. |
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MARCH 2006 |
 | What Do You Do When The CPU Doesn't Deliver? (iDesign Subscribers ) How can you achieve 5x to 15x performance improvements within the power constraints, but with low risk, effort, and expense? |
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Four Steps to Verifying Unpredictable Failure (iDesign Subscribers ) One of the more difficult clock domain crossing (CDC) issues is sequential reconvergence, which occurs when multiple CDC signals are recombined by combinational logic one or more cycles after crossing clock domain boundaries. |
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| Max's Chips and Dips: New EDA Kid on the Block - Athena (iDesign Subscribers ) If this new EDA company's tools are as cool as their logo, they're going to be in good shape! |
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 | Unified Data Model Critical to Addressing Sub-Nanometer DFM/DFY Issues (iDesign Subscribers ) |
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 | How can we ensure that both designs and profits reach their full potential? (iDesign Subscribers ) Incompletely accounting for the physics of thermal effects in the design methodology results in unnecessary design costs due to failed parts. |
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| Max's Chips and Dips: Cool Color from Clairvoyante (iDesign Subscribers ) Clairvoyante's new approach to display technology promises to revolutionize the color displays used for power-conscious hand-held devices like cell phones. |
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FEBRUARY 2006 |
 | Verification Techniques: Going Beyond Simulation (iDesign Subscribers ) FPGA-based prototype boards, combined with empowering design technology, can provide a powerful capability that enables engineers to realize advanced ASIC designs better, faster, and cheaper. |
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 | The Need for Package-Aware Methodology for IC Design (iDesign Subscribers ) A package-aware chip design methodology gives designers a much-needed one-pass package design flow, helping to deliver products to market on time. |
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| Max's Chips and Dips: A new Look at Color Vision (iDesign Subscribers ) Imagine my surprise to discover that much of what I learnt at school as to how color vision works was wrong! |
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JANUARY 2006 |
 | The EDA Ecosystem and Free or Open Source Software (iDesign Subscribers ) This paper addresses the issues of evolving a Free or Open Source Software (F/OSS) initiative within the EDA and silicon industries. |
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| Max's Chips and Dips: SED and OLED displays (iDesign Subscribers ) The next thing in computer displays may well be based on the surface emission display (SED) or organic light emitting display (OLED) technologies. |
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 | Why Double Your Verification Burden? (iDesign Subscribers ) You need a hardware-assisted verification platform that fulfills requirements for hardware regression/debug and software integration/development. |
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 | Taming the Interconnect Beast (iDesign Subscribers ) The process of moving data around a computer chip is quickly becoming intractable; self-timed interconnect offers an elegant solution. |
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A Unified Design Display: Optimizing for Viewability (iDesign Subscribers ) The need for a unified display environment that works across multiple tools within the overall design flow has become a central goal for all of the major EDA vendors. |
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| Max's Chips and Dips: BASIC, Floating-Point, and more... (iDesign Subscribers ) My head is spinning with a plethora of projects, but it's only when you come to create (or describe) something that you realize the holes in your knowledge. |
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DECEMBER 2005 |
 | ESL is all about who does it, not the tools (iDesign Subscribers ) Just like schematics gave way to RTL, anyone who won't move to the next level of abstraction will simply not be able to compete. |
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| Max's Chips and Dips: Ignios and SystemWeaver (iDesign Subscribers ) Managing the complexity of SoCs with multiple uP cores, DSP cores, hardware acceleration engines, and so forth makes the mind boggle. |
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 | There's No Prize for Taking the Long Road (iDesign Subscribers ) As the only ESL Synthesis toolset targeting control logic and complex datapaths, Bluespec enables design teams to accelerate all types of designs, instead of just |
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 | Current-Based Simulation and the Open Core Protocol (OCP) (iDesign Subscribers ) The combination of current-based simulation and the open core protocol results in better products and happier customers. |
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 | Adaptable Chip Designs Keep VoIP Booming (iDesign Subscribers ) Satisfying diverse VoIP application spaces requires an adaptable SoC architecture coupled with targeted IP cores. |
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| Max's Chips and Dips: Conferences, Seminars, and a new DFM Company (iDesign Subscribers ) News regarding a platform modeling workshop, the forthcoming 2006 DVCon conference, and a new player in DFM space. |
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NOVEMBER 2005 |
 | The Resurgence of Custom IC Design (iDesign Subscribers ) Custom IC design is on the increase, because the development of analog designs combined with mixed-signal interfaces cannot be automated. |
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 | The Future of Verification is Open Source Tools (iDesign Subscribers ) It's time to take a hard look at hardware verification languages (HVLs). |
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| Max's Chips and Dips: Got ESL? (iDesign Subscribers ) Good Grief Charlie Brown! Have you noticed how those little scamps at Celoxica keep on popping up in the news these days? |
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 | Preventing the Blame Game (iDesign Subscribers ) In order to break the endless cycle of the blame game, it's time to step back and figure out how to best ensure that the failure will not happen again. |
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 | Graph-Based Physical Synthesis (iDesign Subscribers ) A graph-based physical synthesis methodology enables faster timing closure for today's advanced FPGAs |
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| Max's Chips and Dips: Tensilica's latest and greatest configurable processor (iDesign Subscribers ) New Xtensa 6 processor core provides fastest customization path, lower power, and advanced security provisions |
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OCTOBER 2005 |
 | Verifying Serial RapidIO Interoperability (iDesign Subscribers ) A trio of vendors work together to tackle an extremely tough verification task |
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| Project management is all about planning and execution (iDesign Subscribers ) A good plan contains goals using metrics, with optimal resource usage and realistic schedule estimates. |
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| Max's Chips and Dips: Stop the world, I want to get off! (iDesign Subscribers ) |
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 | Power-Performance Inflection at 90 nm Process Node - FPGAs in Focus (iDesign Subscribers ) The FPGA of choice often depends on which device consumes the least amount of power |
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| Max's Chips and Dips: A bumper issue of iDESIGN (iDesign Subscribers ) More articles and viewpoints than we can handle, and more hot news than you can swing a stick at! |
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 | DFM: Playing without Rules (iDesign Subscribers ) The advent of sub-90 nm process technologies has plunged us into a "tower of Babel" situation! |
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Accelerated Verification of a MATLAB-Driven Digital FIR Filter RTL Design (iDesign Subscribers ) Combining the power of MATLAB for signal generation and analysis with an RTL representation in a high performance emulator |
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 | The Four-Minute Mile and ESL Design (iDesign Subscribers ) Once the mental barrier is broken, everything becomes possible |
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SEPTEMBER 2005 |
 | High-End Chip Designs Require Sophisticated Thermal Analysis (iDesign Subscribers ) Understanding the thermal signature of a chip, including the package-chip interaction, allows both the chip and the package-chip interface to be analyzed for potential problems. |
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| Max's Chips and Dips: Object-Oriented OOPics (iDesign Subscribers ) Is that an OOPic in your pocket, or are you just pleased to see me? |
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 | FPGAs and Structured ASICs: New Solutions for Changing Market Dynamics (iDesign Subscribers ) Verifying a design using state-of-the-art 90 nm FPGAs for prototyping reduces risk. The risk can be further reduced by migrating FPGA-verified design into structured ASICs. |
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| You Can't Get There From Here: A Yankee's Lessons about EDA (iDesign Subscribers ) What perspective and guidance can be culled from the wisdom of people with a rich history and only two seasons: Winter and August? |
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 | The Importance of Sockets in SoC Design (iDesign Subscribers ) The solution to maximizing parallel development effort and core reuse potential requires adopting a well-conceived and specified core-centric socket protocol as the native core interface. |
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| Max's Chips and Dips: Excitement Mounts! (iDesign Subscribers ) New book features virtual computer-calculator |
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AUGUST 2005 |
| The Verification Manager: An Obsolete Entity? (iDesign Subscribers ) Verification is not a task for a compartmentalized team and using point tools and methodologies. Instead, verification needs to be an integrated approach with decisions made at the highest of levels for the good of the entire design team. |
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Advanced FPGA Technology for In-System Verification (iDesign Subscribers ) Including programmable logic analysis cores eases the burden of FPGA designer, reduces design cost, and shortens the design cycle. |
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| Max's Chips and Dips (iDesign Subscribers ) I continue to be amazed (terrified really) by the amount of things I discover that I would never have thought about for myself. |
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Introduction from the Editor-in-Chief (iDesign Subscribers ) iDesign - new online, subscription-based technology publication aimed at EDA and chip designing professionals. |
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| Max's Chips and Dips: Synthesis Challenges Face Structured ASIC Designers (iDesign Subscribers ) |
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JUNE 2005 |
| Max's Chips and Dips (iDesign Subscribers ) I'm like a kid in a sweet shop when it comes to today's incredibly cool EDA tools and electronic technologies and products. |
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Performance Improvements, Hazards, and Resolution Techniques in Pipelined ASICs (iDesign Subscribers ) Adding pipeline stages to a microprocessor core increases performance, but there are a number of potential hazards that need to be overcome in order to achieve a robust and efficient pipelined design. |
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Electronic Design's Super-Size Syndrome (iDesign Subscribers ) |
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 | Structured and Platform ASIC Architectures Mandate Custom Physical Synthesis Solutions (iDesign Subscribers ) The full benefits of structured ASICs can only be realized by having access to custom physical synthesis solutions that take full advantage of their underlying architectures. |
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